Method and apparatus for automatic hierarchical design partitioning

1. A method for designing a system on a target device, the method comprising:

synthesizing the system; and

partitioning the system into a plurality of logical sections, prior to performing placement of the system on the target device, wherein the partitioning comprises evaluating a cost function comprising information derived from synthesizing the system which includes a size of the system, a size of a logical section from the plurality of logic sections, and a number of nodes outside the logical section to be recompiled if the logical section is modified, wherein at least one of the synthesizing and partitioning is performed by a processor.

2. The method of claim 1 , further comprising:

synthesizing the partitioned system;

placing the partitioned system; and

routing the partitioned system.

3. The method of claim 2 , further comprising:

modifying one logical section of the plurality of logical sections of the system; and

re-synthesizing only the one logical section of the system that was modified;

re-placing only the one logical section of the system that was modified; and

re-routing only the one logical section of the system that was modified.

4. The method of claim 1 , further comprising prior to performing routing on the target device, further partitioning the system into additional logical sections utilizing information derived from performing placement of the system.

5. The method of claim 1 , further comprising assigning a physical location for one or more logical sections from the plurality of logical sections.

6. The method of claim 1 , wherein partitioning the system into a plurality of logical sections comprises evaluating a cost function to determine whether to add a component in the system to a logical section.

7. The method of claim 1 , wherein the cost function evaluates whether to add a component in the system to a logical section based upon input from a designer.

8. The method of claim 1 , wherein the cost function evaluates whether a module should be included into a logical section based on its connectivity to other modules.

9. The method of claim 1 , wherein the information derived from synthesizing the system further comprises a number of register interpartition terminals and unregistered interpartition terminals.

10. The method of claim 1 , wherein the information derived from synthesizing the system comprises a number of register interpartition terminals, unregistered interpartition terminals, and connection criticality.

11. The method of claim 1 , wherein the cost function evaluates whether a module should be included into a logical section based on an impact on a size of the module from optimizations forgone by partitioning.

12. The method of claim 1 , wherein the cost function evaluates whether a module should be included into a logical section based on an amount of additional recompilation required resulting from including the module into the logical section.

13. The method of claim 1 , wherein the cost function evaluates whether a module should be included into a logical section based on its likeliness to be modified by a designer.

14. The method of claim 1 , wherein the cost function evaluates whether a module should be included into a logical section based on the placement of other modules.

15. A non-transitory computer-readable medium including a sequence of instructions stored thereon for causing a computer to execute a method, the method comprising:

synthesizing a system; and

partitioning the system into a plurality of logical sections, prior to performing placement of the system on the target device, wherein the partitioning comprises evaluating a cost function comprising information derived from synthesizing the system which includes a size of the system, a size of a logical section from the plurality of logic sections, and a number of nodes outside the logical section to be recompiled if the logical section is modified.

16. The non-transitory computer-readable medium of claim 15 , wherein the information derived from synthesizing the system further comprises a number of register interpartition terminals and unregistered interpartition terminals.

17. A system designer comprising:

a synthesis unit operable to synthesize a system; and

a partition unit operable to partition the system into a plurality of logical section, prior to performing placement of the system on a target device, wherein partitioning comprises evaluating a cost function comprising information derived from synthesizing the system which includes a size of the system, a size of a logical section from the plurality of logic sections, and a number of nodes outside the logical section to be recompiled if the logical section is modified.

18. The system designer of claim 17 further comprising a placement unit operable to perform placement on the system, wherein the partition unit is operable to further partition the system into additional logical sections utilizing information derived from performing placement on the system and prior to performing routing of the system on the target device.