Apparatus and methods for multiple-channel direct memory access

1. An integrated circuit for a multiple-channel direct memory access system, the integrated circuit comprising:

a plurality of direct memory access (DMA) controllers, each one of the plurality of DMA controller corresponding to a different DMA channel;

a channelizer coupled to, and receiving descriptors from, the plurality of DMA controllers;

a plurality of fragmentation circuits in the channelizer, each one of the plurality of fragmentation circuits fragmenting a descriptor from a corresponding DMA controller to generate a plurality of sub-descriptors;

a plurality of priority sort circuits in the channelizer, each one of the plurality of priority sort circuits sorting sub-descriptors from a corresponding fragmentation circuit according to a priority field in the sub-descriptors;

a plurality of priority queues in the channelizer receiving sub-descriptors from the plurality of priority sort circuits, each one of the plurality of priority queues receiving sub-descriptors having an associated value in the priority field;

a scheduler that selects sub-descriptors for transmission from the plurality of priority queues;

a DMA data mover for receiving sub-descriptors from the scheduler and executing the sub-descriptors by causing transfers of data; and

circuitry comprising completion status counters for receiving done status messages indicating successful execution of the sub-descriptors, mapping completed sub-descriptors onto the descriptors, and sending done status messages indicating successful execution of the descriptors to the DMA controllers.

2. The integrated circuit of claim 1 , wherein the priority field comprises a priority bit, and wherein the plurality of priority queues comprises two priority queues.

3. The integrated circuit of claim 1 , wherein the scheduler uses round-robin arbitration where a frequency of transmission from a priority queue depends on a transmit priority weight parameter.

4. The integrated circuit of claim 1 , wherein the DMA data mover comprises a write data mover and a read data mover.

5. The integrated circuit of claim 4 , wherein the read data mover receives data obtained from a source address, and the write data mover sends the data to a destination address.

6. The integrated circuit of claim 1 , further comprising:

a status bus for transmitting the done status messages indicating successful execution of the descriptors from the channelizer to the plurality of DMA controllers.

7. The integrated circuit of claim 1 , further comprising:

a plurality of channel queues in the channelizer for buffering descriptors received from the plurality of DMA controllers.

8. The integrated circuit of claim 7 , further comprising:

multi-channel control registers for receiving commands from the plurality of DMA controllers; and

a descriptor removal circuit for sampling the multi-channel control registers to determine that a descriptor is to be removed from the plurality of channel queues.

9. The integrated circuit of claim 1 , wherein the DMA data mover and the channelizer are implemented in hard-wired circuitry, and wherein the DMA controllers are implemented in electronically-programmed circuitry.

10. A method of providing a direct memory access (DMA) transfers for multiple DMA channels using an integrated circuit, the method comprising:

sending descriptors from a plurality of DMA controllers to a channelizer, each one of the plurality of DMA controllers being associated with a different DMA channel;

fragmenting the descriptors by the channelizer into sub-descriptors; and

sorting the sub-descriptors by the channelizer into a plurality of queues based on a priority field;

using an arbitration procedure by the channelizer to select sub-descriptors for transmission from the plurality of priority queues;

sending selected sub-descriptors from the channelizer to a DMA data mover;

receiving sub-descriptors by the DMA data mover and executing the sub-descriptors by causing movement of data; and

receiving done status messages indicating successful execution of the sub-descriptors, mapping completed sub-descriptors onto the descriptors, and sending done status messages indicating successful execution of the descriptors to the plurality of DMA controllers.

11. The method of claim 10 , wherein the arbitration procedure comprises a round-robin procedure where a frequency of transmission from a priority queue depends on a transmit priority weight parameter.

12. A system for multiple-channel direct memory access (DMA), the system comprising:

a root complex comprising a central processing unit, main memory, and a root port communicatively connected to the main memory and the central processing unit;

a plurality of DMA controllers, each one of the plurality of DMA controller corresponding to a different DMA channel;

a channelizer coupled to, and receiving descriptors from, the plurality of DMA controllers, wherein the channelizer fragments the descriptors to generate sub-descriptors and maps completed sub-descriptors onto the descriptors;

a plurality of priority sort circuits in the channelizer, each one of the plurality of priority sort circuits sorting sub-descriptors according to a priority field in the sub-descriptors;

a plurality of priority queues in the channelizer receiving sub-descriptors from the plurality of priority sort circuits, each one of the plurality of priority queues receiving sub-descriptors having an associated value in the priority field;

a scheduler that selects sub-descriptors for transmission from the plurality of priority queues;

a data mover for receiving and causing execution of the sub-descriptors;

circuitry comprising completion status counters for receiving done status messages indicating successful execution of the sub-descriptors, mapping completed sub-descriptors onto the descriptors, and sending done status messages indicating successful execution of the descriptors to the DMA controllers; and

a data link communicatively interconnecting the root complex and the data mover.

13. The system of claim 12 , wherein the priority field comprises a priority bit, and wherein the plurality of priority queues comprises two priority queues.

14. The system of claim 12 , wherein the scheduler uses round-robin arbitration where a frequency of transmission from a priority queue depends on a transmit priority weight parameter.

15. The system of claim 12 , wherein the data mover comprises a write data mover and a read data mover.

16. The system of claim 15 , wherein the read data mover receives data obtained from a source address, and the write data mover sends the data to a destination address.

17. The system of claim 12 , further comprising:

a status bus for transmitting the done status messages indicating successful execution of the descriptors from the channelizer to the plurality of DMA controllers.

18. The system of claim 12 , further comprising:

a plurality of channel queues in the channelizer for buffering descriptors received from the plurality of DMA controllers.