Techniques for testing programmable interconnect resources

1. A programmable integrated circuit comprising:

rows of circuit blocks;

up driving vertical interconnect resources that each comprises a programmable signal path coupled to at least two of the rows of circuit blocks, and wherein a defect in any one of the up driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in the up driving vertical interconnect resources that originate in different ones of the rows of circuit blocks; and

down driving vertical interconnect resources that each comprises a programmable signal path coupled to at least two of the rows of circuit blocks, and wherein a defect in any one of the down driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in the down driving vertical interconnect resources that originate in different ones of the rows of circuit blocks.

2. The programmable integrated circuit of claim 1 , wherein a defect in any one of the up driving vertical interconnect resources generates a unique failing row signature that allows a failing row of circuit blocks having the defect to be identified and replaced with a redundant row, and wherein a defect in any one of the down driving vertical interconnect resources generates a unique failing row signature that allows a failing row of circuit blocks having the defect to be identified and replaced with a redundant row.

3. The programmable integrated circuit of claim 1 , wherein the up driving vertical interconnect resources route signals between the rows of circuit blocks in a first direction, and wherein the down driving vertical interconnect resources route signals between the rows of circuit blocks in a second direction that is opposite the first direction.

4. The programmable integrated circuit of claim 1 , wherein a first one of the up driving vertical interconnect resources comprises a programmable signal path coupled to two adjacent ones of the rows of circuit blocks, wherein a second one of the up driving vertical interconnect resources comprises a programmable signal path coupled to four adjacent ones of the rows of circuit blocks, and wherein a third one of the up driving vertical interconnect resources comprises a programmable signal path coupled to three of the rows of circuit blocks that are not next to each other.

5. The programmable integrated circuit of claim 4 , wherein a first one of the down driving vertical interconnect resources comprises a programmable signal path coupled to two adjacent ones of the rows of circuit blocks, wherein a second one of the down driving vertical interconnect resources comprises a programmable signal path coupled to four adjacent ones of the rows of circuit blocks, and wherein a third one of the down driving vertical interconnect resources comprises a programmable signal path coupled to three of the rows of circuit blocks that are not next to each other.

6. The programmable integrated circuit of claim 1 , wherein each of the up driving vertical interconnect resources and each of the down driving vertical interconnect resources comprises a multiplexer circuit in one of the rows of circuit blocks that is programmable to drive a signal to adjacent ones of the rows of circuit blocks.

7. The programmable integrated circuit of claim 1 , wherein the circuit blocks in the rows of circuit blocks comprise programmable logic circuits.

8. The programmable integrated circuit of claim 7 , wherein the circuit blocks in the rows of circuit blocks further comprise digital signal processing circuits and memory circuits.