Methods and Apparatus for Profile-Guided Optimization of Integrated Circuits
Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.
1 . A method, comprising:
receiving source code to implement a function in a programmable logic device;
compiling the source code to generate a hardware description for the implementation, wherein the hardware description includes profiling blocks to enable profiling of the implementation;
receiving input data; and
executing the function using the hardware description and the received input data while capturing profiling data, wherein the profiling data comprises:
monitored usage of the programmable logic device using the profiling blocks by analyzing signals to pass through at least a portion of the programmable logic device; and
monitored stall issues within the programmable logic device.
2 . The method of claim 1 , comprising providing a suggestion, via a display, to enable a user to approve a suggested hardware optimization to provide a more optimized implementation of the function based at least in part on the profiling data.
3 . The method of claim 1 , wherein monitored usage comprises monitored transmission of the signals via device traces of the programmable logic device.
4 . The method of claim 1 , wherein the source code comprises OpenCL, C, or C++ programming languages.
5 . The method of claim 1 , wherein the hardware description comprises a register-transfer-level-based hardware description language.
6 . The method of claim 5 , wherein the register-transfer-level-based hardware description language comprises Verilog or Very High Speed Integrated Circuit Hardware Description Language (VHDL).
7 . The method of claim 1 , wherein the profiling data comprises dependent execution of loops.
8 . The method of claim 1 , wherein the profiling data comprises latency information for the implementation.
9 . The method of claim 1 , wherein the profiling data comprises area usage for the implementation.
10 . The method of claim 1 , wherein the profiling data comprises power consumption for the implementation.
11 . The method of claim 1 , comprising updating the implementation based at least in part on the profiling data to generate a more optimized implementation of the function.
12 . The method of claim 11 , wherein updating the implementation comprises updating the source code to include indications of the more optimized implementation.
13 . The method of claim 11 , wherein updating the implementation comprises updating the hardware description to include indications of the more optimized implementation.
14 . Non-transitory, computer-readable medium having stored thereon instructions that, when executed by a processor, are to cause the processor to:
receive source code to implement a function in a programmable logic device;
compile the source code to generate a hardware description for the implementation, wherein the hardware description includes profiling blocks to enable profiling of the implementation;
receive input data; and
execute the function using the hardware description and the received input data while capturing profiling data, wherein the profiling data comprises:
monitored usage of the programmable logic device using the profiling blocks by analyzing signals to pass through at least a portion of the programmable logic device; and
monitored stall issues within the programmable logic device.
15 . The non-transitory, computer-readable medium of claim 14 , wherein the instructions are to cause the processor to provide a suggestion, via a display, to enable a user to approve a suggested hardware optimization to provide a more optimized implementation of the function based at least in part on the profiling data.
16 . The non-transitory, computer-readable medium of claim 15 , wherein the instructions are configured to cause the processor to analyze the profiling data to identify opportunities for hardware optimization in implementing the function, wherein the suggestion is based at least in part on identified opportunities.
17 . The non-transitory, computer-readable medium of claim 16 , wherein the identified opportunities comprise increasing optimization for a target clock frequency.
18 . The non-transitory, computer-readable medium of claim 16 , wherein the identified opportunities comprise increased throughput performance.
19 . A system, comprising:
a programmable logic device;
a processor that, when executing instructions, is to:
receive source code to implement a function in the programmable logic device;
compile the source code to generate a hardware description for the implementation, wherein the hardware description includes profiling blocks to enable profiling of the implementation;
receive input data; and
execute the function using the hardware description and the received input data while capturing profiling data, wherein the profiling data comprises:
monitored usage of the programmable logic device using the profiling blocks by analyzing signals to pass through at least a portion of the programmable logic device; and
monitored stall issues within the programmable logic device.
20 . The system of claim 19 , wherein the processor, when executing the instructions, provide a suggestion, via a display, to enable a user to approve a suggested hardware optimization to provide a more optimized implementation of the function based at least in part on the profiling data.