Apparatus for metastability-hardened storage circuits and associated methods

1. A metastability-hardened storage circuit, comprising a first inverting circuit, having a logical input that is split into a pair of physical inputs.

2. The metastability-hardened storage circuit according to claim 1 , wherein the metastability-hardened storage circuit comprises a latch.

3. The metastability-hardened storage circuit according to claim 1 , wherein the first inverting circuit comprises a gate having at least a pair of inputs.

4. The metastability-hardened storage circuit according to claim 1 , wherein the first inverting circuit comprises an inverter.

5. The metastability-hardened storage circuit according to claim 1 , wherein the first inverting circuit further comprises a logical output that is split into a pair of physical outputs.

6. The metastability-hardened storage circuit according to claim 2 , wherein the metastability-hardened storage circuit comprises a latch.

7. The metastability-hardened storage circuit according to claim 1 , further comprising a second inverting circuit coupled to the first inverting circuit, the second inverting circuit having a logical input that is split into a pair of physical inputs.

8. The metastability-hardened storage circuit according to claim 7 , wherein the second inverting circuit further comprises a logical output that is split into a pair of physical outputs.

9. The metastability-hardened storage circuit according to claim 7 , wherein the second inverting circuit comprises a latch.

10. The metastability-hardened storage circuit according to claim 1 , further comprising a second inverting circuit coupled to the first inverting circuit, the second inverting circuit having a logical output that is split into a pair of physical outputs.

11. The metastability-hardened storage circuit according to claim 10 , wherein the second inverting circuit further comprises a logical input that is split into a pair of physical inputs.

12. The metastability-hardened storage circuit according to claim 10 , wherein the second inverting circuit comprises a latch.

13. A metastability-hardened storage circuit, comprising a first inverting circuit, having a logical output that is split into a pair of physical outputs.

14. The metastability-hardened storage circuit according to claim 13 , wherein the metastability-hardened storage circuit comprises a latch.

15. The metastability-hardened storage circuit according to claim 13 , wherein the first inverting circuit comprises a gate having at least a pair of inputs.

16. The metastability-hardened storage circuit according to claim 13 , wherein the first inverting circuit comprises an inverter.

17. The metastability-hardened storage circuit according to claim 13 , wherein the first storage circuit further comprises a logical input that is split into a pair of physical inputs.

18. The metastability-hardened storage circuit according to claim 17 , wherein the metastability-hardened storage circuit comprises a latch.

19. The metastability-hardened storage circuit according to claim 13 , further comprising a second inverting circuit coupled to the first inverting circuit, the second inverting circuit having a logical input that is split into a pair of physical inputs.

20. The metastability-hardened storage circuit according to claim 19 , wherein the second inverting circuit further comprises a logical output that is split into a pair of physical outputs.

21. The metastability-hardened storage circuit according to claim 19 , wherein the second inverting circuit comprises a latch.

22. The metastability-hardened storage circuit according to claim 13 , further comprising a second inverting circuit coupled to the first inverting circuit, the second inverting circuit having a logical output that is split into a pair of physical outputs.

23. The metastability-hardened storage circuit according to claim 22 , wherein the second inverting circuit further comprises a logical input that is split into a pair of physical inputs.

24. The metastability-hardened storage circuit according to claim 22 , wherein the second inverting circuit comprises a latch.

25. A method of metastability-hardening a storage circuit in an electronic circuit, the method comprising splitting into a pair of physical inputs a logical input of a first inverting circuit in the storage circuit.

26. The method according to claim 25 , further comprising splitting into a pair of physical outputs a logical output of the first inverting circuit.

27. The method according to claim 25 , further comprising splitting into a pair of physical inputs a logical input of a second inverting circuit in the storage circuit.

28. The method according to claim 27 , further comprising splitting into a pair of physical outputs a logical output of the second inverting circuit.

29. The method according to claim 25 , wherein the storage circuit comprises a latch.

30. The method according to claim 27 , wherein the storage circuit comprises a latch.

31. The method according to claim 27 , wherein the storage circuit comprises a flip-flop.

32. An integrated circuit (IC), comprising a first circuit having a first logical input and a first logical output; wherein the first logical output is split into a first high-bias physical output and a first low-bias physical output; and wherein, during a metastable state of the first circuit, an output voltage of the first high-bias physical output is higher than an output voltage of the first low-bias physical output.

33. The integrated circuit (IC) according to claim 32 , further comprising a second circuit having a second logical input and a second logical output; wherein the second logical input is split into a first high-bias physical input coupled to at least one NMOS transistor, and a first low-bias physical input coupled to at least one PMOS transistor.

34. The integrated circuit (IC) according to claim 33 , wherein the first and second circuits form a metastable-hardened storage circuit; wherein the first high-bias output of the first circuit is coupled to the first high-bias input of the said second circuit; and wherein the first low-bias output of the first circuit is coupled to the first low-bias input of the second circuit.

35. The integrated circuit (IC) according to claim 33 , wherein the second logical output is split into a second high-bias physical output, and a second low-bias physical output; and wherein during a metastable state of the second circuit an output voltage of the second high-bias physical output is higher than an output voltage of the second low-bias physical output.

36. The integrated circuit (IC) according to claim 35 , wherein the first high-bias physical output of the first circuit is coupled to a second high-bias physical input of said first circuit; and wherein the first low-bias physical output of said first circuit is coupled to a second low-bias physical input of the first circuit.

37. The integrated circuit (IC) according to claim 36 , wherein the first high-bias physical output of the second circuit is coupled to the second high-bias physical input of the first circuit; and wherein the first low-bias physical output of the first circuit is coupled to the second low-bias physical input of the first circuit.

38. The integrated circuit (IC) according to claim 32 , wherein the first logical output comprises an inverting function of the first logical input.

39. The integrated circuit (IC) according to claim 33 , wherein the second logical output comprises an inverting function of the second logical input.