Filtering with Tensor Structures

1 . An integrated circuit device comprising:

a first tensor circuit comprising a first set of multipliers of a first precision and first summation circuitry; and

a second tensor circuit comprising a second set of multipliers of a second precision and second summation circuitry;

wherein the first tensor circuit and the second tensor circuit are configurable to collectively perform a multiplication operation at a third precision higher than the first precision and the second precision.

2 . The integrated circuit device of claim 1 , comprising:

first bit-shifting circuitry configurable to bit-shift a result from the first tensor circuit in relation to a result from the second tensor circuit; and

first addition circuitry configurable to add the bit-shifted result from the first tensor circuit and the result from the second tensor circuit.

3 . The integrated circuit device of claim 1 , comprising:

a third tensor circuit comprising a third set of multipliers of the first precision and third summation circuitry; and

a fourth tensor circuit comprising a fourth set of multipliers of the second precision and second summation circuitry;

wherein the first tensor circuit, the second tensor circuit, the third tensor circuit, and the fourth tensor circuit are configurable to collectively perform a multiplication operation at a fourth precision higher than the first precision and the second precision.

4 . The integrated circuit device of claim 3 , wherein:

the first tensor circuit and the second tensor circuit are within a first digital signal processing block; and

the third tensor circuit and the fourth tensor circuit are within a second digital signal processing block;

wherein the integrated circuit device comprises:

a dedicated connection between the first digital signal processing block and the second digital signal processing block;

bit shifting circuitry configurable to bit-shift a result from the first digital signal processing block in relation to a result from the second digital signal processing block; and

addition circuitry configurable to sum the bit-shifted result from the first digital signal processing block and the result from the second digital signal processing block.

5 . The integrated circuit device of claim 3 , wherein the multiplication operation comprises obtaining a product equal to multiplying a first value by a second value, wherein:

the first tensor circuit is configurable to multiply a first part of the first value by a first part of the second value;

the second tensor circuit is configurable to multiply the first part of the first value by a second part of the second value;

the third tensor circuit is configurable to multiply a second part of the first value by the first part of the second value; and

the fourth tensor circuit is configurable to multiply the second part of the first value by the second part of the second value.

6 . The integrated circuit device of claim 4 , comprising:

first bit-shifting circuitry configurable to bit-shift a first result from the first tensor circuit relative to a second result from the second tensor circuit;

second bit-shifting circuitry configurable to bit-shift a third result from the third tensor circuit relative to a fourth result from the fourth tensor circuit;

first addition circuitry configurable to add the first shifted result and the second result to obtain a fifth result;

second addition circuitry configurable to add the third shifted result and the fourth result to obtain a sixth result;

third bit-shifting circuitry configurable to bit-shift the fifth result relative to the sixth result; and

third addition circuitry configurable to add the fifth shifted result and the sixth result to obtain the product equal to multiplying the first value by the second value.

7 . The integrated circuit device of claim 3 , wherein the first tensor circuit, the second tensor circuit, the third tensor circuit, the fourth tensor circuit, the first bit-shifting circuitry, the second bit-shifting circuitry, the first addition circuitry, the second addition circuitry, the third bit-shifting circuitry, and the third addition circuitry are formed in hardened circuitry.

8 . The integrated circuit device of claim 3 , wherein the first precision is 8 bits, the second precision is 8 bits, and the fourth precision is 16×16 bits.

9 . The integrated circuit device of claim 1 , wherein the first precision is equal to the second precision.

10 . The integrated circuit device of claim 1 , wherein the first precision is different from the second precision.

11 . Filter circuitry comprising:

a plurality of tensor circuits configurable to multiply sets of components of input data with sets of components of weights;

bit-shifting circuitry configurable to shift a portion of the results output by the tensor circuits to produce shifted results; and

addition circuitry configurable to sum the shifted portion of the results with the non-shifted results to produce an output signal.

12 . The filter circuitry of claim 11 , wherein a first section of the filter circuitry comprises a first precision and a second section of the filter circuitry comprises a second precision.

13 . The filter circuitry of claim 11 , wherein a first set of the plurality of tensor circuits respectively comprise multipliers with inputs of the first precision and the second precision, wherein the first precision is different from the second precision.

14 . The filter circuitry of claim 11 , wherein:

the sets of components of the input data comprise:

a first data component holding a first set of most significant bits of a first input data value; and

a second data component holding a second set of least significant bits of the first input data value; and

the sets of components of the weights comprise:

a first weight component holding a first set of most significant bits of a first weight value; and

a second weight component holding a second set of least significant bits of the first weight value.

15 . The filter circuitry of claim 11 , wherein the tensor circuits comprise a first set of registers and a second set of registers, wherein the first set of registers is configurable to store a first portion of the sets of components of the input data or the sets of components of the weights to use to perform multiplication operations while a second portion of the sets of components of the input data or the sets of components of the weights are loaded via the second set of registers.

16 . The filter circuitry of claim 11 , wherein the tensor circuits comprise a first set of registers and a second set of registers and are configurable to implement a decimation filter, wherein the first set of registers is configurable to store a first portion of the sets of components of the input data representing one of even data samples and odd data samples, and wherein the second set of registers is configurable to store a second portion of the sets of components of the input data representing the other of the even data samples and odd data samples, wherein the tensor circuits are configurable to perform multiplication operations based on the storage from the first set of registers, and wherein the first set of registers is configurable to shift data to the second set of registers and the second set of registers is configurable to shift data to the first set of registers between multiplication operations.

17 . A programmable logic device comprising:

programmable logic circuitry configurable to implement soft logic circuits; and

embedded digital signal processing blocks configurable to perform mathematical operations based on hardened logic circuitry, wherein at least some of the digital signal processing blocks comprise:

a tensor circuit comprising:

a set of multiplier circuits configurable to multiply respective multiplicand values with multiplier values;

a first set of registers configurable to store a first set of the multiplier values;

a second set of registers configurable to store a second set of the multiplier values;

a first set of multiplexers, wherein each multiplexer of the first set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to one of the set of multiplier circuits;

a second set of multiplexers, wherein each multiplexer of the second set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to a next one of the first set of registers; and

a third set of multiplexers, wherein each multiplexer of the first set of multiplexers receives inputs from one of the first set of registers and one of the second set of registers and selectively outputs to a next one of the second set of registers.

18 . The programmable logic device of claim 17 , wherein the tensor circuit is configurable to be used in a decimation filter, wherein the first set of the multiplier values corresponds to even or odd data samples and the second set of the multiplier values corresponds to the other of even or odd data samples.

19 . The programmable logic device of claim 17 , wherein the tensor circuit is configurable to be used in a finite impulse response filter that operates on the first set of multiplier values while the second set of the multiplier values is being loaded.

20 . The programmable logic device of claim 17 , wherein the tensor circuit has a first precision or a second precision and wherein multiple digital signal processing blocks are configurable to collectively perform a multiplication operation at a third precision higher than the first precision and the second precision.