Method and system for dynamic table line encoding

1. An apparatus comprising:

a first input port operative to receive a first data value;

a first memory device operative to look up a second data value based on the first data value, wherein the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and wherein the memory device is operative to be configured according to a plurality of line encoding schemes; and

a first output port operative to provide an output signal, wherein the output signal comprises one or more data values including the second data value.

2. The apparatus of claim 1 , wherein the encoded representation of the first data value is encoded according to a line encoding scheme.

3. The apparatus of claim 2 , wherein the memory device is operative to be configured from a first line encoding scheme to a second line encoding scheme, wherein the first line encoding scheme is selected from the group consisting of: 8b10b, Interlaken 64-67, Peripheral Component Interconnect Express (PCIE), and Ethernet 64-66, and wherein the second line encoding scheme is different from the first line encoding scheme.

4. The apparatus of claim 1 , wherein the memory device is comprised of a random access memory (RAM) or a plurality of RAMs including composition logic.

5. The apparatus of claim 1 , wherein the first output port is a link in a transceiver.

6. The apparatus of claim 1 further comprising a second input port, a second memory device, and a second output port.

7. The apparatus of claim 6 , wherein first memory device and the second memory device are operative to look up data values according to a first encoding scheme and a second encoding scheme.

8. The apparatus of claim 7 , wherein the first encoding scheme is different from the second encoding scheme.

9. The apparatus of claim 1 further comprising a processor, wherein the processor is operative to implement an encoding scheme in the first memory device based on a transmission error rate associated with the output signal.

10. The apparatus of claim 9 , wherein the transmission error rate is a bit error rate.

11. A method comprising:

receiving a first data value at a first input port of a memory device;

identifying a second data value based on the first data value, wherein the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and wherein the memory device is operative to be configured according to a plurality of line encoding schemes; and

providing one or more data values including the second data value at a first output port of the memory device.

12. The method of claim 11 , wherein the encoded representation of the first data value is encoded according to a first encoding scheme.

13. The method of claim 12 further comprising reconfiguring the memory device to operate in accordance with a second encoding scheme.

14. The method of claim 13 further comprising:

reconfiguring the memory device to operate in accordance with a third encoding scheme; and

determining whether the first, second, or third encoding scheme results in a lowest bit error rate.

15. The method of claim 14 further comprising reconfiguring the memory device to operate in accordance with the determined encoding scheme.

16. The method of claim 11 further comprising:

detecting a data transmission error at a receiver, wherein the receiver is operative to receive the one or more data values from the first output port of the memory device;

recording a data value and first symbol associated with the data transmission error;

identifying a total number of errors associated with the symbol; and

associating a second symbol with the first data value.

17. A non-transitory computer readable storage medium having computer code embodied therein, the computer readable storage medium comprising:

computer code for receiving a first data value at a first input port of a memory device;

computer code for identifying a second data value based on the first data value, wherein the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and wherein the memory device is operative to be configured according to a plurality of line encoding schemes; and

computer code for providing one or more data values including the second data value at a first output port of the memory device.

18. The non-transitory computer readable storage medium of claim 17 , wherein the encoded representation of the first data value is encoded according to a first encoding scheme.

19. The non-transitory computer readable storage medium of claim 18 further comprising:

computer code for reconfiguring the memory device to operate in accordance with a second encoding scheme;

computer code for reconfiguring the memory device to operate in accordance with a third encoding scheme; and

computer code for determining whether the first, second, or third encoding scheme results in a lowest bit error rate.

20. The non-transitory computer readable storage medium of claim 17 further comprising:

computer code for detecting a data transmission error at a receiver, wherein the receiver is operative to receive the one or more data values from the first output port of the memory device;

computer code for recording a data value and first symbol associated with the data transmission error;

computer code for identifying a total number of errors associated with the symbol; and

computer code for associating a second symbol with the first data value.