Programmable high-speed voltage-mode differential driver
View Patent ↗A voltage-mode differential driver is disclosed. The differential driver includes two driver arms, each driver arm including a variable-impedance driver for driving a single-ended output signal. Each variable-impedance driver comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.
1. A differential driver for driving a differential signal, the differential driver comprising:
a first driver arm comprising a first variable-impedance driver for driving a first single-ended output signal of the differential signal; and
a second driver arm comprising a second variable-impedance driver for driving a second single-ended output signal of the differential signal;
a first re-timing block providing a first plurality of re-timed signals to the first variable-impedance driver; and
a second re-timing block providing a second plurality of re-timed signals to the second variable-impedance driver,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit and a driver circuit.
2. The differential driver of claim 1 , wherein each said re-timing block comprises multiple re-timing slices, and wherein each said re-timing slice corresponds to a tap of a pre-emphasis filter.
3. The differential driver of claim 2 , wherein each said re-timing slice comprises:
a first register for receiving a first half-rate data signal;
a second register for receiving a second half-rate data signal; and
a multiplexer for multiplexing the first and second half-rate data signals into a full-rate data signal,
wherein a first single-ended clock signal of a differential clock signal is received by a clock input of the first register, and a second single-ended clock signal of the differential clock signal is received by a clock input of the second register.
4. The differential driver of claim 2 further comprising:
a first programmable inverter which receives an output of a first re-timing slice corresponding to a pre-tap of the pre-emphasis filter; and
a second programmable inverter which receives an output of a second re-timing slice corresponding to a second post (P 2 ) tap of the pre-emphasis filter.
5. The differential driver of claim 4 further comprising:
a plurality of 2:1 multiplexers that each receive outputs of a third re-timing slice corresponding to a first post (P 1 ) tap of the pre-emphasis filter and a fourth re-timing slice corresponding to a main tap of the pre-emphasis filter.
6. The differential driver of claim 1 further comprising:
a first programmable inversion multiplexer positioned between the first re-timing block and the first variable-impedance driver; and
a second programmable inversion multiplexer positioned between the second re-timing block and the second variable-impedance driver.
7. The differential driver of claim 1 , wherein the pre-driver circuit is configurable into one of four states: a first state which configures the driver circuit to a driver mode; a second state which configures the driver circuit to a tri-state mode; a third state which configures the driver circuit to a first on-chip termination mode; and a four state which configures the driver circuit to a second on-chip termination mode.
8. The differential driver of claim 1 , wherein the driver circuit comprises a variable-unit driver circuit.
9. A differential driver for driving a differential signal, the differential driver comprising:
a first driver arm comprising a first variable-impedance driver for driving a first single-ended output signal of the differential signal; and
a second driver arm comprising a second variable-impedance driver for driving a second single-ended output signal of the differential signal;
a first delay control circuit which receives an input differential clock signal and outputs a first skew-corrected differential clock signal for the first driver arm; and
a second delay control circuit which receives the input differential clock signal and outputs a second skew-corrected differential clock signal for the second driver arm,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit and a driver circuit.
10. A differential driver for driving a differential signal, the differential driver comprising:
a first driver arm comprising a first variable-impedance driver for driving a first single-ended output signal of the differential signal; and
a second driver arm comprising a second variable-impedance driver for driving a second single-ended output signal of the differential signal;
a first duty cycle distortion (DCD) control circuit which receives an input differential clock signal and outputs a first DCD-corrected differential clock signal for the first driver arm; and
a second DCD control circuit which receives the input differential clock signal and outputs a second DCD-corrected differential clock signal for the second driver arm,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit and a driver circuit.
11. The differential driver of claim 10 further comprising:
a first DCD detection circuit which receives a first single-ended output signal from the first variable-impedance driver and provides a first DCD control signal to the first DCD control circuit; and
a second DCD detection circuit which receives a second single-ended output signal from the second variable-impedance driver and provides a second DCD control signal to the second DCD control circuit.
12. A differential driver for driving a differential signal, the differential driver comprising:
a first driver arm comprising a first variable-impedance driver for driving a first single-ended output signal of the differential signal; and
a second driver arm comprising a second variable-impedance driver for driving a second single-ended output signal of the differential signal,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit and a driver circuit,
wherein the driver circuit comprises a variable-unit driver circuit, and
wherein the variable-unit driver circuit comprises:
a plurality of PMOS transistor sets having different numbers of PMOS transistors arranged in parallel; and
a plurality of NMOS transistor sets having different numbers of NMOS transistors arranged in parallel.
13. The differential driver of claim 12 , wherein each said transistor set is controlled by a control signal that controls whether the transistor set is used or un-used.
14. The differential driver of claim 1 further comprising:
an on-chip termination circuit positioned between outputs of the first and second variable-impedance drivers.
15. A method for driving a differential signal, the method comprising:
providing a first plurality of re-timed signals to a first variable-impedance driver in a first driver arm; and
providing a second plurality of re-timed signals to a second variable-impedance driver in a second driver arm,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit and a driver circuit.
16. The method of claim 15 further comprising:
generating the first plurality of re-timed signals using a first re-timing block; and
generating the second plurality of re-timed signals using a second re-timing block,
wherein each said re-timing block comprises multiple re-timing slices, and wherein each said re-timing slice corresponds to a tap of a pre-emphasis filter.
17. The method of claim 15 , wherein the driver circuit comprises a variable-unit driver circuit, further comprising:
programmably configuring the variable-unit driver circuit of each driver slice to have a driving strength equal to a number of driving units.
18. The method of claim 15 further comprising:
adjusting a output voltage swing by changing a common mode reference voltage applied to on-chip termination circuitry between the first driver arm and the second driver arm.
19. An integrated circuit comprising:
a first data output pin;
a second data output pin;
a first driver arm comprising a first variable-impedance driver for driving a first single-ended output signal of a differential signal onto the first data output pin; and
a second driver arm comprising a second variable-impedance driver for driving a second single-ended output signal of the differential signal onto the second data output pin;
a first re-timing block providing a first plurality of re-timed signals to the first variable-impedance driver; and
a second re-timing block providing a second plurality of re-timed signals to the second variable-impedance driver,
wherein each said variable-impedance driver comprises multiple driver slices, each driver slice including a pre-driver circuit and a driver circuit.