Deskew across high speed data lanes
View Patent ↗Methods and structures are disclosed for aligning high speed data across a plurality of lanes. In one embodiment, a method and integrated circuit (“IC”) is provided for receiving and aligning scrambled training data across a plurality of data lanes before the data is descrambled. In some implementations, a known scrambled training pattern is different in each lane and alignment includes comparing incoming training data in each lane to different known scrambled training patterns in each lane. In some implementations, after scrambled data is aligned and then descrambled, it is checked against a known unscrambled training pattern to make sure that alignment of the scrambled training data was correct. In an alternative embodiment, data is descrambled before being aligned, but deskew circuitry output is monitored to determine if a training pattern ends at the same time across the plurality of lanes being aligned. If not, then data in a lane for which the training pattern ends earliest is delayed by an amount corresponding to the length of one or more cycles of the training pattern.
1. A method of multi-lane data communications comprising:
receiving scrambled training data on an integrated circuit (“IC”) in each of a plurality of lanes; and
aligning the scrambled training data across the plurality of lanes using a known pattern of scrambled training data, wherein aligning comprises delaying data in a lane for which a data alignment point of the known pattern has reached a designated register until corresponding alignment points for data in other lanes are at corresponding designated registers in those other lanes.
2. The method of claim 1 wherein the known pattern of scrambled training data includes different known patterns of scrambled training data for each of the plurality of lanes.
3. The method of claim 1 , wherein aligning determines preliminary alignment, the method further comprising confirming alignment by descrambling preliminarily aligned training data for each of the plurality of lanes and determining whether descrambled training data matches a known pattern of descrambled training data.
4. The method of claim 3 wherein if descrambled preliminarily aligned training data for each of the plurality of lanes does not match the known pattern of descrambled training data, the method is repeated.
5. The method of claim 1 wherein, for each lane, the designated register is a memory element at a read location of a first-in-first-out circuit (“FIFO”).
6. Receive circuitry in an integrated circuit (“IC”) adapted for multi-lane data communication comprising:
deskew circuitry in each of a plurality of data lanes;
descrambler circuitry in each of the plurality of data lanes coupled to receive and descramble data from the deskew circuitry; and
state machine circuitry adaptable to control the deskew circuitry to align scrambled data received by the IC across the plurality of data lanes prior to the data being descrambled by the descrambler circuitry.
7. The receive circuitry of claim 6 wherein the state machine circuitry is adaptable to control the deskew circuitry by:
monitoring incoming scrambled training data received by the deskew circuitry;
using a known pattern of scrambled training data to determine whether an alignment point of the received scrambled training data has reached a designated register of the deskew circuitry; and
delaying the received scrambled data in the deskew circuitry of the particular lane until corresponding alignment points of received scrambled training data in all other lanes have reached corresponding designated registers of corresponding deskew circuitry in all other lanes.
8. The receiver of claim 6 wherein, for each lane, the designated register is a memory element at a read location of a first-in-first-out circuit (“FIFO”).
9. The receive circuitry of claim 6 wherein the state machine circuit is adaptable to determine whether descrambled data output by the descrambler circuitry matches a known pattern of descrambled training data.
10. An integrated circuit (“IC”) comprising the receive circuitry of claim 6 .
11. A data processing system comprising the IC of claim 10 .
12. A method of multi-lane data communications comprising:
receiving scrambled training data on an integrated circuit (“IC”) in each of a plurality of lanes;
descrambling the training data;
aligning descrambled training data to an alignment point of a known pattern of descrambled training data;
determining if an end of the training data reaches designated registers in all of the plurality of lanes on a same clock cycle; and
if the end of the training data does not reach designated registers in all of the plurality of lanes on the same clock cycle, delaying data by a length of the known pattern of descrambled training data in any lane for which the end of the training data reached a designated register prior to other lanes.
13. The method of claim 12 further comprising after delaying data by a length of the known pattern of descrambled training data, if the end of the training pattern is still not at designated registers in all of the plurality of lanes on a same clock cycle, delaying data again by a length of the known pattern of descrambled training data in any lane for which the end of the training data reached a designated register prior to other lanes.
14. The method of claim 12 wherein aligning comprises:
for a particular lane, using a known pattern of descrambled training data to determine whether an alignment point of the received and descrambled training data has reached a designated register;
determining whether corresponding alignment points for descrambled training data in all other lanes have reached corresponding designated registers; and
if corresponding alignment points for descrambled training data in all other lanes have not reached corresponding designated registers, delaying data for the particular lane.
15. The method of claim 12 wherein alignment points for descrambled training data are a middle transition of the known pattern of descrambled training data.
16. The method of claim 12 wherein, for each lane, the designated register is a memory element at a read location of a first-in-first-out circuit (“FIFO”).
17. Receive circuitry in an integrated circuit (“IC”) adapted for multi-lane data communication comprising:
descrambler circuitry in each of the plurality of data lanes coupled to receive and descramble data;
deskew circuitry in each of a plurality of data lanes coupled to receive descrambled data; and
state machine circuitry adaptable to control the deskew circuitry to align training data received by the IC across the plurality of data lanes by:
aligning the training data at an alignment point of a known pattern of the training data;
determining whether an end of the training data is aligned across the plurality of lanes; and
if the end of the training data does not reach designated registers in all of the plurality of lanes on the same clock cycle, delaying data by a length of the known pattern of descrambled training data in any lane for which the end of the training data reached the receive circuitry prior to other lanes.
18. The receive circuitry of claim 17 wherein the state machine is adaptable to align the training data at an alignment point of a known pattern of the training data by:
for a particular lane, using a known pattern of descrambled training data to determine whether an alignment point of the received and descrambled training data has reached a designated register;
determining whether corresponding alignment points for descrambled training data in all other lanes have reached corresponding designated registers; and
if corresponding alignment points for descrambled training data in all other lanes have not reached corresponding designated registers, delaying data for the particular lane.
19. An integrated circuit (“IC”) comprising the receive circuitry of claim 17 .
20. A data processing system comprising the IC of claim 19 .