Method and system for operating a circuit
View Patent ↗Operation of a programmable circuit is described. A circuit including a plurality of multiplexers may be used to perform at least one operation on a plurality of signals. The at least one operation may be performed by the multiplexers using a select line coupled to or shared by the multiplexers. Each input of the circuit may couple to a respective output of a plurality of logic elements. As such, the circuit may be used to perform at least one operation on signals supplied from a plurality of logic elements, thereby expanding the functionality of at least one logic element coupled to the circuit and/or increasing the number of logic elements and other resources available for implementing user designs or performing other functions.
1. A method of operating a circuit, said method comprising:
accessing a plurality of signals using a plurality of inputs of said circuit, wherein said plurality of signals is output by a plurality of logic elements, wherein said circuit comprises a plurality of outputs and a first plurality of multiplexers, wherein a first input of said plurality of inputs corresponds to a first output of said plurality of outputs, and wherein a second input of said plurality of inputs corresponds to a second output of said plurality of outputs;
accessing at least one signal using a select line coupled to said first plurality of multiplexers; and
performing, responsive to said accessing said at least one signal, at least one operation on said plurality of signals using said first plurality of multiplexers, and wherein said performing said at least one operation is operable to expand functionality of said plurality of logic elements, and wherein said at least one operation comprises communicating a first signal from said first input to said second output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal from said second input to a third output of said plurality of outputs using a second multiplexer of said first plurality of multiplexers.
2. The method of claim 1 , wherein said performing further comprises changing, during a runtime of said circuit, a respective state associated with each multiplexer of said first plurality of multiplexers.
3. The method of claim 1 , wherein said at least one operation comprises communicating a first signal from said first input to said first output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal from said second input to said second output using a second multiplexer of said first plurality of multiplexers.
4. The method of claim 1 , wherein said performing further comprises communicating said second signal to a third input of said plurality of inputs, and wherein said at least one operation further comprises communicating said second signal from said third input to a fourth output of said plurality of outputs using a third multiplexer of said first plurality of multiplexers.
5. The method of claim 1 further comprising:
configuring, before runtime of said circuit, a second plurality of multiplexers using at least one select line coupled to said second plurality of multiplexers; and
communicating, using said second plurality of multiplexers based on said configuring, a second plurality of signals from said plurality of inputs to said plurality of outputs by bypassing said first plurality of multiplexers.
6. The method of claim 1 , wherein said first and second inputs are adjacent inputs, wherein said at least one operation comprises communicating a first signal of said plurality of signals from said first input to said second output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal of said plurality of signals from said second input to said second output using said first multiplexer.
7. The method of claim 1 , wherein said accessing said plurality of signals further comprises accessing a first signal of said plurality of signals using said first input, wherein said operation comprises a logical operation on said first signal and said at least one signal, and wherein said performing further comprises outputting on said first output a second signal associated with a result of said logical operation.
8. A circuit comprising:
a plurality of inputs and a plurality of outputs, wherein a first input of said plurality of inputs corresponds to a first output of said plurality of outputs, and wherein a second input of said plurality of inputs corresponds to a second output of said plurality of outputs;
a first plurality of multiplexers coupled to said plurality of inputs and said plurality of outputs; and
a select line coupled to said first plurality of multiplexers and operable to change a respective state associated with each multiplexer of said first plurality of multiplexers, and
wherein said first plurality of multiplexers is further operable to perform, responsive to accessing at least one signal using said select line, at least one operation on a plurality of signals accessed using said plurality of inputs, wherein said plurality of signals is output by a plurality of logic elements, and wherein performance of said at least one operation is operable to expand functionality of said plurality of logic elements; and
a second plurality of multiplexers coupled to at least one select line other than said select line coupled to said first plurality of multiplexers, wherein said second plurality of multiplexers is operable to communicate, responsive to configuration using said at least one select line, a second plurality of signals from said plurality of inputs to said plurality of outputs by bypassing said first plurality of multiplexers.
9. The circuit of claim 8 , wherein said at least one operation comprises communicating a first signal from said first input to said first output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal from said second input to said second output using a second multiplexer of said first plurality of multiplexers.
10. The circuit of claim 8 , wherein said at least one operation comprises communicating a first signal from said first input to said second output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal from said second input to a third output of said plurality of outputs using a second multiplexer of said first plurality of multiplexers.
11. The circuit of claim 10 , wherein said second signal is communicated to a third input of said plurality of inputs, and wherein said at least one operation further comprises communicating said second signal from said third input to a fourth output of said plurality of outputs using a third multiplexer of said first plurality of multiplexers.
12. The circuit of claim 8 , wherein said first and second inputs are adjacent inputs, wherein said at least one operation comprises communicating a first signal of said plurality of signals from said first input to said second output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal of said plurality of signals from said second input to said second output using said first multiplexer.
13. The circuit of claim 8 , wherein a first multiplexer of said first plurality of multiplexers is operable to access a first signal of said plurality of signals using said first input, wherein said operation comprises a logical operation on said first signal and said at least one signal, and wherein said first multiplexer is further operable to output on said first output a second signal associated with a result of said logical operation.
14. An integrated circuit comprising:
a processor;
a memory coupled to said processor;
a plurality of logic elements; and
a circuit coupled to said plurality of logic elements, said circuit comprising:
a plurality of inputs and a plurality of outputs, wherein a first input of said plurality of inputs corresponds to a first output of said plurality of outputs, and wherein a second input of said plurality of inputs corresponds to a second output of said plurality of outputs;
a first plurality of multiplexers coupled to said plurality of inputs and said plurality of outputs; and
a select line coupled to said first plurality of multiplexers and operable to change a respective state associated with each multiplexer of said first plurality of multiplexers, and
wherein said processor is operable to configure said first plurality of multiplexers to perform, responsive to accessing at least one signal using said select line, at least one operation on a plurality of signals accessed using said plurality of inputs, wherein said plurality of signals is output by said plurality of logic elements, and wherein performance of said at least one operation is operable to expand functionality of said plurality of logic elements; and
wherein said first and second inputs are adjacent inputs, wherein said at least one operation comprises communicating a first signal of said plurality of signals from said first input to said second output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal of said plurality of signals from said second input to said second output using said first multiplexer.
15. The integrated circuit of claim 14 , wherein said at least one operation comprises communicating a first signal from said first input to said first output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal from said second input to said second output using a second multiplexer of said first plurality of multiplexers.
16. The integrated circuit of claim 14 , wherein said at least one operation comprises communicating a first signal from said first input to said second output using a first multiplexer of said first plurality of multiplexers, and wherein said at least one operation further comprises communicating a second signal from said second input to a third output of said plurality of outputs using a second multiplexer of said first plurality of multiplexers.
17. The integrated circuit of claim 16 , wherein said second signal is communicated to a third input of said plurality of inputs, and wherein said at least one operation further comprises communicating said second signal from said third input to a fourth output of said plurality of outputs using a third multiplexer of said first plurality of multiplexers.
18. The integrated circuit of claim 14 , wherein said circuit further comprises:
a second plurality of multiplexers coupled to at least one select line other than said select line coupled to said first plurality of multiplexers, wherein said second plurality of multiplexers is operable to communicate, responsive to configuration using said at least one select line, a second plurality of signals from said plurality of inputs to said plurality of outputs by bypassing said first plurality of multiplexers.
19. The integrated circuit of claim 14 , wherein a first multiplexer of said first plurality of multiplexers is operable to access a first signal of said plurality of signals using said first input, wherein said operation comprises a logical operation on said first signal and said at least one signal, and wherein said first multiplexer is further operable to output on said first output a second signal associated with a result of said logical operation.