Protocol error monitoring on an interface between hard logic and soft logic
View Patent ↗Techniques and mechanisms detect deviations from a protocol being used to communicate between devices, for example, in hard logic (e.g., implemented as an ASIC or fixed circuitry) and soft logic (e.g., implemented in configurable logic of an FPGA). Techniques and mechanisms are described for detecting a variety of deviations from a protocol.
1. A method for monitoring transactions between a hard logic system and a configurable logic system, the method comprising:
receiving, on a monitoring circuit, a first transaction addressed to a first slave on the configurable logic system, the first transaction received from a master on the hard logic system;
transmitting the first transaction to the first slave;
receiving a first return transaction from the configurable logic system;
determining an error has occurred in the configurable logic system; and
transmitting an error message to the master.
2. The method of claim 1 , wherein determining the error has occurred includes determining that a length of data of the first return transaction is incorrect.
3. The method of claim 1 , wherein determining the error has occurred includes determining that the first return transaction is from a second slave on the configurable logic system.
4. The method of claim 1 , further comprising:
receiving, on the monitoring circuit, a second transaction addressed to a second slave from the master on the hard logic system, the second transaction received after the first transaction;
transmitting the second transaction to the second slave; and
wherein determining an error has occurred includes determining that a second return transaction associated with the second transaction is received before the first return transaction, and the error message indicating that the second return transaction is an error.
5. The method of claim 4 , further comprising:
transmitting a second error message to the master, the second error message indicating that the first transaction resulted in an error.
6. The method of claim 1 , wherein determining the error has occurred includes determining that the first return transaction is not returned within a time window.
7. The method of claim 6 , wherein a duration of the time window is increased upon an increase in errors detected in the configurable logic system.
8. The method of claim 1 , further comprising:
adding the first transaction to a queue of outstanding transactions; and
determining that the queue of transactions does not exceed a threshold of outstanding transactions.
9. The method of claim 1 , wherein the monitoring circuit is on the configurable logic system.
10. A circuit for monitoring transactions between a hard logic system and a configurable logic system, the circuit comprising:
a monitoring circuit configured to:
receive a first transaction addressed to a first slave on the configurable logic system, the first transaction received from a master on the hard logic system;
transmit the first transaction to the first slave;
receive a first return transaction from the configurable logic system;
determine an error has occurred in the configurable logic system; and
transmit an error message to the master.
11. The circuit of claim 10 , wherein determining the error has occurred includes determining that a length of data of the first return transaction is incorrect.
12. The circuit of claim 10 , wherein determining the error has occurred includes determining that the first return transaction is from a second slave on the configurable logic system.
13. The circuit of claim 10 , wherein the monitoring circuit is further configured to:
receive a second transaction addressed to a second slave from the master on the hard logic system, the second transaction received after the first transaction;
receive the second transaction to the second slave; and
wherein determining an error has occurred includes determining that a second return transaction associated with the second transaction is received before the first return transaction, and the error message indicating that the second return transaction is an error.
14. The circuit of claim 13 , further configured to:
transmit a second error message to the master, the second error message indicating that the first transaction resulted in an error.
15. The circuit of claim 10 , wherein determining the error has occurred includes determining that the first return transaction is not returned within a time window.
16. The circuit of claim 15 , wherein a duration of the time window is increased upon an increase in errors detected in the configurable logic system.
17. The circuit of claim 10 , wherein the monitoring circuit is further configured to:
add the first transaction to a queue of outstanding transactions; and
determine that the queue of transactions does not exceed a threshold of outstanding transactions.
18. The circuit of claim 10 , wherein the monitoring circuit is on the configurable logic system.
19. The circuit of claim 10 , wherein the hard logic system and the configurable logic system are on the same device.
20. The circuit of claim 10 , wherein the hard logic system and the soft logic system are on separate devices.
21. A circuit for monitoring transactions between a hard logic system and a configurable logic system, the circuit comprising:
means for receiving, on a monitoring circuit, a first transaction addressed to a first slave on the configurable logic system, the first transaction received from a master on the hard logic system;
means for transmitting the first transaction to the first slave;
means for receiving a first return transaction from the configurable logic system;
means for determining an error has occurred in the configurable logic system; and
means for transmitting an error message to the master.