Methods and structures for handling integrated circuits
View Patent ↗In one embodiment, a tray that includes a dielectric frame structure, a re-adherable pad and a marking is disclosed. The dielectric frame structure includes a recessed region where the re-adherable pad is formed. A plurality of integrated circuits is placed on a re-adherable surface of the re-adherable pad. The marking on the dielectric frame that is reflective of a given input-output pin position for each integrated circuit in the plurality of integrated circuits in the tray. In addition to that, two methods are also disclosed. First, a method of handling the integrated circuits using the tray is disclosed. Second, a method of forming the tray is also disclosed.
1. A method for handling integrated circuits, comprising:
receiving a tray having a re-adherable surface on which the integrated circuits are placed;
with automated equipment, removing some of the integrated circuits from the re-adherable surface of the tray; and
with the automated equipment, identifying a pin marker that is available on the tray, wherein the pin marker indicates locations of more than one integrated circuit in the placed integrated circuits.
2. The method as defined in claim 1 , wherein remaining integrated circuits are still in contact with the re-adherable material.
3. The method as defined in claim 1 , wherein the tray conforms to specifications of a Joint Electron Device Equipment Council (JEDEC) standard.
4. The method as defined in claim 1 , further comprising:
with the automated equipment, positioning a pick and place tool above a first of the integrated circuits based on the information of the pin marker.
5. The method as defined in claim 4 , further comprising:
with the automated equipment, wherein the first integrated circuit is removed using the pick and place tool.
6. The method as defined in claim 1 , wherein the integrated circuits are placed within a recess of the tray, and wherein the integrated circuits are arranged in a plurality of rows within the recess.
7. A method for forming an apparatus that includes a tray, comprising:
forming a frame structure on the tray, wherein the frame structure includes a top surface and a recessed opening at the top surface;
placing re-adherable material within the recessed opening, wherein a top surface of the re-adherable material is coplanar with the top surface of the frame structure; and
placing a plurality of integrated circuits on the re-adherable material according to a predetermined arrangement.
8. The method as defined in claim 7 , wherein dimensions of the tray is according to a Joint Electron Device Engineering Council (JEDEC) standard.
9. The method as defined in claim 7 , further comprising:
selecting the re-adherable material from adhesive materials ranging from an adhesive level of one to seven, wherein the adhesive levels of one to seven indicate levels of increasing adhesive strength, wherein the adhesive level of one indicates relatively low adhesive strength, and wherein the adhesive level of seven indicates relatively high adhesive strength.
10. The method as defined in claim 7 , wherein the predetermined arrangement includes an arrangement that conforms to the JEDEC standard.
11. The method as defined in claim 7 , further comprising:
forming a first pin marker on a corner edge of the tray.
12. An apparatus, comprising:
a tray;
a frame structure formed on the tray, wherein the frame structure includes a top surface and a recessed opening at the top surface;
re-adherable material placed in the recessed opening, wherein a top surface of the re-adherable material is coplanar with the top surface of the frame structure; and
a plurality of integrated circuits placed on the re-adherable material according to a predetermined arrangement; and
a marking on the frame structure that is reflective of a given input-output pin position for each integrated circuit in the plurality of integrated circuits in the tray.
13. The apparatus as defined in claim 12 , wherein the frame structure has dimensions specified within a Joint Electron Device Engineering Council (JEDEC) standard.
14. The apparatus as defined in claim 12 , wherein the re-adherable material has an adhesive level that ranges from level one to level seven, wherein the adhesive levels of one to seven indicate levels of increasing adhesive strength, wherein the adhesive level of one indicates relatively low adhesive strength, and wherein the adhesive level of seven indicates relatively high adhesive strength.
15. The apparatus as defined in claim 12 , further comprising:
an electrostatic discharge (ESD) tape placed on the plurality of integrated circuits, wherein the ESD tape reduces damage of the plurality of integrated circuits from ESD events.
16. The apparatus as defined in claim 12 , wherein the frame structure comprises an injection molded structure.
17. The apparatus as defined in claim 12 , wherein the recessed opening comprises an etched region within the tray.