Channel sizing for inter-kernel communication

1. A tangible, non-transitory, machine-readable-medium, comprising machine readable instructions to:

access, via a compiler, a high level program comprising instructions to be programmed on an integrated circuit;

convert, via the compiler, the high level program into a low level program to be implemented on the integrated circuit, wherein the low level program comprises a first kernel, a second kernel, and an inter-kernel channel that enables inter-channel communication between the first kernel and the second kernel; wherein the first kernel and the second kernel each comprise a digital circuit implementation that bridge the low level program and executable instructions to be performed by the integrated circuit;

identify, via the compiler: a latency of the inter-kernel channel, predication between the first kernel and the second kernel, a scheduling imbalance between data processing of the first kernel and data processing of the second kernel, or any combination thereof;

modify, via the compiler, a size of the inter-kernel channel, by:

adding additional depth to the inter-kernel channel until a depth of the inter-kernel channel is greater than the latency;

adding additional depth to the inter-kernel channel until the depth of the inter-kernel channel includes enough space to store an implemented channel capacity and additional data received during an amount of time equal to the latency;

adjusting the depth of the inter-kernel channel based upon a calculation of a number of threads that need to be held in the inter-kernel channel, in the worst case, when one of the first kernel or the second kernel is able to consume more threads than the other;

or any combination thereof; and

provide, via the compiler, the low level program with the modified size of the inter-kernel channel to the integrated circuit for implementation on the integrated circuit;

wherein the inter-kernel channel is sized based upon the predication of the inter-kernel channel reads, inter-kernel channel writes, or both.

2. The machine-readable-medium of claim 1 , wherein the instructions to size the inter-kernel channel comprise instructions to:

size the inter-kernel channel based upon a latency of the inter-kernel channel.

3. The machine-readable-medium of claim 2 , wherein the instructions to size the inter-kernel channel comprise instructions to:

size the inter-kernel channel, such that a minimum depth of the inter-kernel channel is greater than the latency of the inter-kernel channel.

4. The machine-readable-medium of claim 1 , wherein the instructions to size the inter-kernel channel comprise instructions to:

size the inter-kernel channel, such that a capacity of the inter-kernel channel is equal to or greater than an initial capacity of the inter-kernel channel plus a latency of the inter-kernel channel.

5. The machine-readable-medium of claim 1 , wherein the instructions to size the inter-kernel channel comprise instructions to:

size the inter-kernel channel based upon at least two of: a latency of the inter-kernel channel, predication, and scheduling imbalances of the first and second kernels.

6. The machine-readable-medium of claim 1 , wherein the low level program comprises a plurality of inter-kernel channels, and the machine readable instructions comprise instructions to size two or more of the plurality of inter-kernel channels, the sizing, based upon a latency of a respective inter-kernel channel being sized, predication of the respective inter-kernel channel being sized, scheduling imbalances between kernels at endpoints of the respective inter-kernel channel being sized, or any combination thereof.

7. A tangible, non-transitory, machine-readable-medium, comprising machine readable instructions to:

access, via a compiler, a high level program comprising instructions to be programmed on an integrated circuit;

convert, via the compiler, the high level program into a low level program to be implemented on the integrated circuit, wherein the low level program comprises a first kernel, a second kernel, and an inter-kernel channel that enables inter-channel communication between the first kernel and the second kernel; wherein the first kernel and the second kernel each comprise a digital circuit implementation that bridge the low level program and executable instructions to be performed by the integrated circuit;

identify, via the compiler: a scheduling imbalance between data processing of the first kernel and data processing of the second kernel;

modify, via the compiler, a size the inter-kernel channel based upon scheduling imbalances between the first kernel and the second kernel, by:

adjusting a depth of the inter-kernel channel based upon a calculation of a number of threads that need to be held in the inter-kernel channel, in the worst case, when one of the first kernel or the second is able to consume more threads than the other; and

provide, via the compiler, the low level program with the modified size of the inter-kernel channel to the integrated circuit for implementation on the integrated circuit;

wherein the instructions to size the inter-kernel channel comprise instructions to:

construct an integer linear programming problem to size the inter-kernel channel, by:

determining a maximum latency to reach a read portion of the inter-kernel channel (hereinafter max_latency(read));

determining a maximum latency to reach a write portion of the inter-kernel channel (hereinafter max_latency(write));

determining a minimum capacity that can be live prior to a read at the inter-kernel channel (hereinafter min_capacity(read));

determining a minimum capacity that can be live prior to a write to a kernel from the inter-kernel channel (hereinafter min_capacity(write));

determining a first kernel scheduling slack variable, the first kernel scheduling slack variable representing a delayed start of the first kernel relative to the second kernel;

determining a second kernel scheduling slack variable, the second kernel scheduling slack variable representing a delayed start of the second kernel relative to the first kernel;

applying a constraint for the inter-kernel channel, such that a slack variable from the first kernel scheduling slack variable or the second kernel scheduling slack variable corresponding to a reading kernel minus a slack variable from the first kernel scheduling slack variable or the second kernel scheduling slack variable corresponding to a writing kernel is greater than or equal to the max_latency(read) minus the min_capacity(write);

defining and minimizing a cost function for the first kernel and the second kernel, wherein the cost function for the first kernel and the second kernel is defined as a sum of widths of all inter-kernel channels having a read in the respective first kernel or second kernel minus a sum of all inter-kernel channels having a write in the respective first kernel or second kernel; and

setting a depth of the inter-kernel channel to equal to the slack variable for the reading kernel minus the slack variable for the writing kernel plus max_latency(read) minus min_capacity(write).

8. An integrated circuit (IC) device comprising:

programmable logic comprising an implementation of one or more inter-kernel channels that communicatively couple first and second kernels that each comprise a digital circuit implementation that bridge a low level program and executable instructions to be performed by the integrated circuit;

wherein at least a subset of the one or more inter-kernel channels was sized by a compiler or programmable logic design software based upon predication of a respective inter-kernel channel being sized, by:

identifying: a latency of the one or more inter-kernel channels, predication between the first kernel and the second kernel, a scheduling imbalance between data processing of the first kernel and data processing of the second kernel, or any combination thereof; and

adding additional depth to the inter-kernel channel until a depth of the inter-kernel channel is greater than the latency;

adding additional depth to the inter-kernel channel until the depth of the inter-kernel channel includes enough space to store an implemented channel capacity and additional data received during an amount of time equal to the latency;

adjusting the depth of the inter-kernel channel based upon a calculation of a number of threads that need to be held in the inter-kernel channel, in the worst case, when one of the first kernel or the second is able to consume more threads than the other;

or any combination thereof.

9. The IC device of claim 8 , wherein the programmable logic comprises at least one partial reconfiguration (PR) block comprising a physical location on the IC that can be reconfigured during runtime of the IC.

10. The IC device of claim 8 , wherein at least a subset of the one or more inter-kernel channels comprise a first-in-first-out (FIFO) buffer.

11. The IC device of claim 8 , wherein the at least a subset of the one or more inter-kernel channels is sized based upon a latency of a respective inter-kernel channel being sized.

12. The IC device of claim 8 , wherein the at least a subset of the one or more inter-kernel channels is sized based upon scheduling imbalances of kernels connected to a respective inter-kernel channel being sized.

13. The IC device of claim 8 , wherein the at least a subset of the one or more inter-kernel channels is sized based upon a latency of a respective inter-kernel channel being sized, predication of the respective inter-kernel channel being sized, and scheduling imbalances of kernels connected to the respective inter-kernel channel being sized.

14. A method, comprising:

identifying, via a compiler: a latency of one or more inter-kernel channels, predication between a first kernel and a second kernel, a scheduling imbalance between data processing of the first kernel and data processing of the second kernel, or any combination thereof, wherein the one or more inter-kernel channels communicatively couple the first kernel to the second kernel and the first kernel and the second kernel each comprise a digital circuit implementation that bridge a low level program and executable instructions to be performed by an integrated circuit;

sizing, via the compiler, one or more inter-kernel channels, by:

adding additional depth to the inter-kernel channel until a depth of the inter-kernel channel is greater than the latency;

adding additional depth to the one or more inter-kernel channels until the depth of the inter-kernel channel includes enough space to store an implemented channel capacity and additional data received during an amount of time equal to the latency;

adjusting the depth of the one or more inter-kernel channels based upon a calculation of a number of threads that need to be held in the inter-kernel channel, in the worst case, when one of the first kernel or the second is able to consume more threads than the other; or

any combination thereof; and

providing, via the compiler, sizing information regarding the sizing to an integrated circuit for implementation of the inter-kernel channel on the integrated circuit, according to the sizing;

wherein the sizing of the one or more inter-kernel channels is based upon a latency of a respective inter-kernel channel being sized, predication of the respective inter-kernel channel being sized, scheduling imbalances of kernels connected to the respective inter-kernel channel being sized, or any combination thereof; and the method further comprising sizing at least one inter-kernel channel based upon the scheduling imbalances using an integer linear programming problem, by:

determining a maximum latency to reach a read portion of the at least one inter-kernel channel (hereinafter max_latency(read));

determining a maximum latency to reach a write portion of the at least one inter-kernel channel (hereinafter max_latency(write));

determining a minimum capacity that can be live prior to a read at the at least one inter-kernel channel (hereinafter min_capacity(read));

determining a minimum capacity that can be live prior to a write to a kernel from the at least one inter-kernel channel (hereinafter min_capacity(write));

determining a first kernel scheduling slack variable, the first kernel slack variable representing a delayed start of a first kernel relative to a second kernel, where the first kernel and second kernel are associated with the at least one inter-kernel channel;

determining a second kernel scheduling slack variable, the second kernel slack variable representing a delayed start of the second kernel relative to the first kernel;

applying a constraint for the at least one inter-kernel channel, such that a slack variable from the first kernel scheduling slack variable or the second kernel scheduling slack variable corresponding to a reading kernel minus a slack variable from the first kernel scheduling slack variable or the second kernel scheduling slack variable corresponding to a writing kernel is greater than or equal to the max_latency(read) minus the min_capacity(write);

defining and minimizing a cost function for the first kernel and the second kernel, wherein the cost function for the first kernel and the second kernel is defined as a sum of widths of all inter-kernel channels having a read in the respective first kernel or second kernel minus a sum of all inter-kernel channels having a write in the respective first kernel or second kernel; and

setting a depth of the at least one inter-kernel channel to equal to the slack variable for the reading kernel minus the slack variable for the writing kernel plus max_latency(read) minus min_capacity(write).