Systems and methods for reducing static and total power consumption in programmable logic device architectures
View Patent ↗A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, and period following routing of the programmable logic device.
1. A programmable logic device including a heterogeneous routing pool, the pool comprising:
areas of low-power logic signal routing; and
areas of high-power logic signal routing;
wherein:
the power consumption of each of the areas is taken into account in designating one of the areas for portions of a logic design to be programmed.
2. The programmable logic device of claim 1 , wherein the routing pool has three or more gradations of low-, medium- and high-power logic signal routing resources.
3. The programmable logic device of claim 1 , wherein the logic cells have a heterogeneous power profile.
4. A digital processing system comprising:
processing circuitry;
a memory coupled to said processing circuitry; and
a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
5. A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
6. The printed circuit board defined in claim 5 further comprising:
memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.
7. The printed circuit board defined in claim 6 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.
8. The programmable logic device of claim 1 wherein, in said routing pool, areas of higher-power logic signal routing resources include wires that are longer than wires in areas of lower-power logic signal routing resources.
9. The programmable logic device of claim 1 wherein, in said routing pool, areas of higher-power logic signal routing resources include wires that are narrower than wires in areas of lower-power logic signal routing resources.
10. The programmable logic device of claim 1 wherein, in said routing pool, areas of higher-power logic signal routing resources include wires that are closer together than are wires in areas of lower-power logic signal routing resources.
11. The programmable logic device of claim 1 wherein, in said routing pool, areas of higher-power logic signal routing resources include wires driven by transistors that are larger than transistors that drive wires in areas of lower-power logic signal routing resources.
12. A heterogeneous routing pool for a programmable logic device, the heterogeneous routing pool comprising:
areas of low-power logic signal routing; and
areas of high-power logic signal routing;
wherein:
the power consumption of each of the areas is taken into account in designating one of the areas for portions of a logic design to be programmed.
13. The heterogeneous routing pool of claim 12 , said routing pool having three or more gradations of low-, medium- and high-power logic signal routing resources.
14. The heterogeneous routing pool of claim 12 wherein areas of higher-power logic signal routing resources include wires that are longer than wires in areas of lower-power logic signal routing resources.
15. The heterogeneous routing pool of claim 12 wherein areas of higher-power logic signal routing resources include wires that are narrower than wires in areas of lower-power logic signal routing resources.
16. The heterogeneous routing pool of claim 12 wherein areas of higher-power logic signal routing resources include wires that are closer together than are wires in areas of lower-power logic signal routing resources.
17. The heterogeneous routing pool of claim 12 wherein areas of higher-power logic signal routing resources include wires driven by transistors that are larger than transistors that drive wires in areas of lower-power logic signal routing resources.
18. A digital processing system comprising:
processing circuitry;
a memory coupled to said processing circuitry; and
a programmable logic device having a heterogeneous routing pool as defined in claim 12 coupled to the processing circuitry and the memory.
19. A printed circuit board on which is mounted a programmable logic device having a heterogeneous routing pool as defined in claim 12 .
20. The printed circuit board defined in claim 19 further comprising:
memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.
21. The printed circuit board defined in claim 20 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.