Resource-saving circuit structures for deeply pipelined systolic finite impulse response filters

1. Circuitry accepting a data input and an enable input and generating an output based on the data input, the circuitry comprising:

an input stage circuit including:

an input register accepting the enable input;

an enable register configured to accept the enable input and generate a delayed enable signal for flow control of the circuitry;

an intermediate stage circuit that is coupled to the input stage circuit including:

a first systolic register that is operated without any enable connection at the steady state of the circuitry,

a second systolic register sequentially connected to the first systolic register, wherein the second systolic register is connected to the enable register to accept the delayed enable signal, and

a multiplier connected in series with the first and second systolic registers, wherein the multiplier is configured to generate a product value; and

an output stage circuit that is coupled to the intermediate stage circuit and includes an adder that calculates the output based at least in part on the product value.

2. The circuitry of claim 1 , wherein the multiplier is placed between the input stage circuit and the first systolic register.

3. The circuitry of claim 1 , wherein the multiplier is placed between the second systolic register and the output stage circuit.

4. The circuitry of claim 1 , further comprising a group delay register placed between the intermediate stage circuit and the output stage circuit,

wherein the group delay register is operated without any enable connection.

5. The circuitry of claim 4 , further comprising a balancing delay register to delay the enable input to balance the group delay register.

6. The circuitry of claim 5 , wherein the group delay register is connected to the adder in the output stage circuit, and the balancing delay register is connected to an output register in the output stage circuit.

7. Circuitry accepting a data input and an enable input and generating a finite impulse response output based on the data input, the circuitry comprising:

an input stage circuit including an input register;

an enable register that receives the enable input and generates a delayed enable signal;

an intermediate stage circuit that is coupled to the input stage circuit including:

first and second systolic registers that are operated without any enable connection at the steady state of the circuitry,

a third systolic register sequentially connected to the first systolic register, wherein the third systolic register is connected to the enable register to accept the delayed enable signal,

a first multiplier connected in series with the first and third systolic registers;

a second multiplier connected in series with the second systolic register; and

an output stage circuit operatively connected to the intermediate stage circuit, including:

an adder circuit including a single adder, or a pair of adders without any physical element separating the pair of adders.

8. The circuitry of claim 7 , wherein the input register is enabled by an enable input.

9. The circuitry of claim 7 , further comprising a plurality of pipelines coupled between the intermediate stage circuit and the output stage circuit.

10. The circuitry of claim 9 , further comprising:

an output register in the output stage circuit that is coupled to the adder circuit; and

a delay register connected to the enable register, wherein:

the delay register creates a delayed enable signal to balance the plurality of the pipelines; and

the output register accepts the delayed enable signal.

11. The circuitry of claim 7 , further comprising:

a plurality of pipelines to pipeline operations of the adder circuit.

12. The circuitry of claim 11 , further comprising a delay register connected to the output stage circuit and the enable register, wherein

the delay register creates a delayed enable signal to balance the plurality of the pipelines.

13. The circuitry of claim 11 , wherein the output stage circuit receives an exogenous delay input to balance the plurality of pipelines.

14. The circuitry of claim 7 , further comprising:

a plurality of pipelines disposed with a physical element within the circuitry to pipeline an operation of the physical element, wherein

the physical element is different from any of the first multiplier, the second multiplier, the adder circuit; and

a delay register to balance the plurality of pipelines.

15. The circuitry of claim 7 , wherein the single adder calculates an output sum based at least in part on product values calculated by the first multiplier and the second multiplier, and a value of the data input without any additional adder.

16. A pipelined systolic finite impulse response (FIR) filter, comprising:

an input stage circuit including an input register, wherein

the input register accepts an enable input;

an enable delay register that accepts the enable input and generates a delayed enable signal;

a FIR calculation circuit that is coupled to the input stage circuit, including:

a first systolic register that is operated without any enable connection at the steady state of the circuitry,

a second systolic register sequentially connected to the first systolic register, wherein the second systolic register is connected to the enable delay register to accept the delayed enable signal, and

a multiplier connected in series with the first and second systolic registers;

an output stage circuit, including an adder that calculates an output sum; and

a plurality of pipeline registers to pipeline part of an operation of the FIR calculation circuit or the adder, wherein

each pipeline stage of the pipelined systolic FIR filter has a separate enable register without fanning out the enable input for each pipeline stage.

17. The circuitry of claim 16 , further comprising a plurality of delay registers being disposed between the input stage circuit and the output stage circuit,

wherein the plurality of delay registers creates a latency in the enable input equivalent to a depth of the plurality of pipelines.

18. The circuitry of claim 16 , wherein the separate enable register at each pipeline stage generates a delayed enable signal to enable a respective pipeline stage.

19. The circuitry of claim 16 , wherein the multiplier is placed between the input register and the first systolic register.

20. The circuitry of claim 16 , wherein the output stage circuit is retimed by a retiming register to operate without any additional adder other than the adder.

21. A method for operating a pipelined systolic finite impulse response (FIR) filter, comprising:

receiving, at an input register, a data input signal and an enable input signal, wherein

the input register generates a delayed data input signal;

receiving, at an enable register, the enable input signal, wherein the enable register generates a delayed enable signal;

transmitting the delayed data input signal to a first systolic register operatively connected to the input register, wherein

the first systolic register is operated without any enable connection;

transmitting a first systolic register output from the first systolic register to a second systolic register, wherein the second systolic register accepts the delayed enable signal from the enable register;

calculating, at a multiplier, a product value based at least in part on a second systolic register output from the second systolic register; and

generating, at an adder, an output sum based least in part on the product value.

22. The method of claim 21 , further comprising:

pipelining, via a plurality of pipeline registers disposed in connection with the multiplier or the adder, an operation of the multiplier or the adder.