Programmable logic device with a self-power down mechanism
View Patent ↗Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.
1. A method for reducing power consumption in a programmable logic device (PLD), comprising:
detecting a quiescent state in the PLD through logic circuitry of the PLD;
applying a timer to track an idle time of the quiescent state;
storing a previous known state into a memory module with at least one sector, wherein the at least one sector in the memory module is allocated for storing configuration information of the previous known state, the at least one sector partitioned into a plurality of sections, each section having a plurality of addresses;
initiating a power down operation in the quiescent state PLD in response to the tracked idle time meeting or exceeding a maximum idle time; and
placing the PLD in a reduced power consumption state.
2. The method of claim 1 , wherein the PLD is connected to an external circuit, wherein the external circuit controls the power supply to the PLD.
3. The method of claim 1 , wherein the initiating a power down operation is performed by a controller element within the PLD.
4. The method of claim 1 , wherein putting the PLD in a reduced power consumption state reduces standby current in the PLD to less than about 1 uA.
5. The method of claim 1 , further comprising:
generating a quiescent state signal based on monitoring input signals of the PLD, wherein the quiescent state signal is applied in tracking the idle time.
6. The method of claim 1 , wherein the storing a previous known state into a memory module comprises:
examining a first bit of a first address from a first section of the at least one sector;
storing the configuration information of the previous known state into a first address from a second section of the sector, the first address in the second section corresponding to a first bit of the first address;
shifting data stored in the first address by at least one bit; and
writing to a second bit of the first address.
7. The method of claim 6 , wherein the first section with the plurality of addresses is a header section, and wherein the addresses in the header section are used to locate corresponding addresses in the second section.
8. The method of claim 6 , wherein the first bit of the first address is the most significant bit (MSB) of the address.
9. The method of claim 6 , further comprising:
erasing the at least one of the sectors that is used to hold configuration information of the previous known state, wherein the erasing is done before the writing to the second bit of the first address.
10. The method of claim 1 , further comprising:
detecting an active signal within the PLD;
initiating a power up operation in the PLD;
placing the PLD into an operative state, wherein the PLD is in a higher power consumption state; and
retrieving the previous known state from the memory module; and
restoring the PLD to the previous known state.
11. The method of claim 10 , further comprising:
activating the PLD based on an input signal.
12. The method of claim 10 , wherein the retrieving the previous known state from the memory module comprises:
locating a most recent valid bit in an address from a first section of the at least one of the sectors; and
loading the previous known state from a corresponding address in a second section, wherein the corresponding address in the second section is located by the most recent valid bit in the address from the first section.
13. The method of claim 1 , wherein each method operation is embodied as program instructions on a machine-readable medium.
14. The method of claim 1 , wherein the timer is programmable as to the maximum idle time.
15. The method of claim 1 , wherein input activity to the PLD resets the timer.
16. A method of operating an integrated circuit, comprising:
activating a timer that is operable to identify a quiescent state in the integrated circuit;
storing a last known state of at least a portion of the integrated circuit into an on-chip memory module of the integrated circuit in response to the timer identifying the quiescent state in the integrated circuit; and
placing the integrated circuit into a reduced power consumption state in response to completing the storing the last known state, using a controller element coupled to the timer.
17. The method of claim 16 , further comprising:
placing the integrated circuit into an active power consumption state in response to receiving an active signal, using the controller element coupled to the timer; and
restoring the last known state of the at least a portion of the integrated circuit in response to receiving the active signal and the placing the integrated circuit into the active power consumption state.
18. The method of claim 16 , wherein:
the integrated circuit includes a programmable logic device (PLD);
the on-chip memory module includes a flash memory; and
the last known state is stored into a predefined location in the on-chip memory.
19. The method of claim 16 , wherein the controller element controls a power supply that is external to the integrated circuit.
20. The method of claim 16 , further comprising:
resetting the timer in response to input activity to the integrated circuit.