Programmable logic device with a self-power down mechanism
Apparatuses for reducing power consumption in a programmable logic device (PLD) with a self power down mechanism are disclosed. Methods and a machine readable medium for restoring a prior known state are provided. The prior known state is stored in a memory module before the PLD is powered down and the same state is restored from the memory module when the PLD is powered up. The memory module may be an internal or an external non-volatile or volatile memory source. One sector of the memory may be used to store the previous known state. The memory sector can be partitioned into different sections. One section may be used as a header section associated with a data storage section. Partitioning the memory sector into different sections and utilizing multiple addresses from each section ensure less read and write cycles during the powering down and the powering up of the PLD.
1. An integrated circuit (IC) with
a self-power down mechanism, comprising:
an application module;
a timer coupled to an input signal of the application module, the timer operable to identify a quiescent state in the IC;
a controller element coupled to the timer and the application module; and
a memory module coupled to the controller element.
2. The IC of claim 1 , wherein the IC is a programmable logic device (PLD).
3. The IC of claim 2 , wherein the timer is programmable.
4. The IC of claim 1 , wherein the memory module is an on-chip non-power dependent module.
5. The IC of claim 1 , wherein the memory module is partitioned into a plurality of sectors, wherein at least one of the plurality of sectors is used to store a previous known state.
6. A power control system for an integrated circuit (IC), comprising:
an onboard flash memory;
a timeout detector coupled to an input signal of the IC, wherein the timeout detector is operable to identify a quiescent state in the IC, and wherein the timeout detector is operable to initiate storage of a last known state of the onboard flash memory responsive to detecting the quiescent state;
a controller element coupled to the timeout detector and the onboard flash memory; and
circuitry coupled to the controller element, wherein the circuitry is operable to control power supply to the IC.
7. The power control system of claim 6 , wherein the controller element is operable to transmit a signal to the circuitry to initiate a power down operation.
8. The power control system of claim 6 , wherein the circuitry is external to the IC.
9. The power control system of claim 6 , wherein the circuitry comprises:
a power source;
a transistor coupled to the power source;
a first resistor, wherein a first terminal of the first resistor is coupled to the power source and the transistor and a second terminal is coupled to a first input terminal of the circuitry and a first input pin of the IC;
a second resistor, wherein a first terminal of the second resistor is coupled to the transistor, the power source, and the first resistor, and a second terminal is coupled to a second input pin of the IC; and
a third resistor, wherein a first terminal of the third resistor is coupled to the transistor and an output pin of the IC and a second terminal is coupled to a second input terminal of the circuitry.
10. The circuitry of claim 9 , wherein the second and third resistors are operable to drive the transistor.
11. The circuitry of claim 9 , wherein the transistor is a P-channel MOSFET operable to control power supply to the IC.
12. The circuitry of claim 9 , wherein the second input terminal receives a signal to drive the transistor to power up the IC.
13. The circuitry of claim 9 , wherein the second resistor is a pull-up resistor.
14. The circuitry of claim 6 , wherein the IC is a programmable logic device (PLD).
15. The circuitry of claim 6 , wherein the onboard flash memory is non-volatile memory.