Integrated circuit (IC) clocking techniques
View Patent ↗Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.
1. A circuit comprising:
a divider circuit operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal;
a recovery circuit coupled to the divider circuit, wherein the recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal; and
a phase aligner circuit coupled to the recovery circuit, the phase aligner circuit having the second signal as an input, wherein the phase aligner circuit is operable to align a phase of the second signal with a phase of the recovered clock signal based on the first ready signal.
2. The circuit of claim 1 , wherein the recovery circuit comprises a phase-locked loop (PLL) circuit operable to lock the phase of the recovered clock signal to a phase of the second signal.
3. The circuit of claim 1 , wherein the circuit is a clock data recovery (CDR) circuit coupled to an external circuit, and wherein the first signal is a clock signal that is received from the external circuit.
4. The circuit of claim 1 , wherein the first signal is a serial clock signal, and wherein the second signal is a parallel clock signal.
5. The circuit of claim 1 further comprises a transmitter circuit operable to transmit a second ready signal to an external circuit.
6. The circuit of claim 5 , wherein the second ready signal is similar to the first signal.
7. The circuit of claim 1 further comprising:
a switching circuit having a first input coupled to the recovery circuit and a second input coupled to the phase aligner circuit, wherein the switching circuit is operable to transmit signals from one of the first input or the second input based on the first ready signal.
8. The circuit of claim 1 , wherein the phase aligner circuit includes a delay buffer, a comparator, and a feedback controller.
9. The circuit of claim 8 , wherein the feedback controller receives an output of the comparator and transmits a signal to the delay buffer.
10. The circuit of claim 1 , wherein the phase aligner circuit compares the second signal to a recovered clock signal.
11. A method of operating an integrated circuit (IC) comprising:
receiving a preamble signal at a first speed from an external component;
dividing the preamble signal to generate a first signal at a second speed;
locking a phase of a second signal to a phase of the first signal to generate a third signal, wherein the second signal is generated within a recovery circuit in the IC;
aligning a phase of the third signal with the phase of the first signal, via an aligner having the first signal as an input; and
clocking the IC with the aligned third signal.
12. The method of claim 11 , wherein the aligning comprises:
determining a phase difference between the first signal and the third signal; and
applying a delay to the third signal based on the phase difference.
13. The method of claim 11 , wherein the preamble signal is a serial clock signal, and wherein the dividing the preamble signal comprises:
converting the serial clock signal to a parallel clock signal to generate the first signal.
14. The method of claim 11 further comprising:
outputting a ready signal after the IC is clocked with the aligned third signal; and
receiving a data stream from the external component after the clocking.
15. The method of claim 14 , wherein the outputting the ready signal comprises:
transmitting the preamble signal from the IC to the external component.
16. The method of claim 11 further comprising:
placing the IC in a first operating mode prior to the clocking; and
placing the IC in a second operating mode prior to the receiving the data stream from the external component, wherein the first operating mode is operable to route the first and third signals through a first path in the recovery circuit in the IC, and wherein the second operating mode is operable to route the data stream through a second path in the recovery circuit.
17. The method of claim 11 , wherein the receiving the preamble signal comprises:
receiving a training pattern from the external component, and wherein the IC is clocked based on the training pattern.
18. The method of claim 11 , further comprising:
determining a frequency of the second signal.
19. The method of claim 11 , wherein the preamble signal is a differential signal.
20. The method of claim 11 , wherein the preamble signal is received through a differential buffer.