Reference clock architecture for integrated circuit device
View Patent ↗A clocking arrangement for transceivers in an integrated circuit device includes a plurality of fractionally adjustable phase-locked loops. Each respective one of the fractionally adjustable phase-locked loops generates a respective transmit frequency for a respective one of the transceivers. There is a respective clock-data recovery module in a receive portion of each respective one of the transceivers, and each respective clock-data recovery module includes a respective fractionally adjustable frequency-lock loop. There is a reference clock input providing a reference clock for a plurality of the fractionally adjustable phase-locked loops and the fractionally adjustable frequency-lock loops. The reference clock input can be a sole reference clock input providing a reference clock for all of the adjustable phase-locked frequency-lock loops. Alternatively, the reference clock input can include a plurality of separate reference clock inputs, each providing a separate reference clock to a predetermined subset of the adjustable phase-locked or frequency-lock loops.
1. A clocking arrangement for transceivers in an integrated circuit device, said clocking arrangement comprising:
a plurality of fractionally adjustable phase-locked loops, each respective one of said fractionally adjustable phase-locked loops being for generating a respective transmit frequency for a respective one of said transceivers;
a respective clock-data recovery module in a receive portion of each respective one of said transceivers, each respective clock-data recovery module including a respective fractionally adjustable frequency-lock loop; and
a reference clock input providing a reference clock for said plurality of fractionally adjustable phase-locked loops and said fractionally adjustable frequency-lock loops.
2. The clocking arrangement of claim 1 wherein:
input data having a data rate is input to each respective clock-data recovery module;
said respective frequency-lock loop of said respective clock-data recovery module locks to a rate close to said data rate; and
said respective clock-data recovery module further comprises a respective data-lock loop that locks to said data rate after said respective frequency-lock loop locks to said rate close to said data rate.
3. The clocking arrangement of claim 1 wherein:
said reference clock input is a sole reference clock input that provides a reference clock for said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops; and
said clocking arrangement further comprises a single reference clock conductor for conducting said reference clock from said single reference clock input to said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops.
4. The clocking arrangement of claim 1 wherein:
said reference clock input comprises a plurality of separate reference clock inputs, each of which provides a separate reference clock to a first predetermined subset of said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops; and
said clocking arrangement further comprises a reference clock bus including a respective separate reference clock conductor for conducting each of the separate reference clocks from a respective one of said separate reference clock inputs directly to said respective predetermined subset of said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops.
5. The clocking arrangement of claim 4 wherein said predetermined subset of said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops comprises only adjustable phase-locked loops.
6. The clocking arrangement of claim 5 wherein said predetermined subset of said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops comprises said plurality of fractionally adjustable phase-locked loops.
7. The clocking arrangement of claim 4 wherein said predetermined subset of said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops comprises only adjustable frequency-lock loops.
8. The clocking arrangement of claim 7 wherein said predetermined subset of said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops comprises said adjustable frequency-lock loops.
9. An integrated circuit device, comprising:
a plurality of transceivers;
a plurality of fractionally adjustable phase-locked loops, each respective one of said fractionally adjustable phase-locked loops being for generating a respective transmit frequency for a respective one of said transceivers;
a respective clock-data recovery module in a receive portion of each respective one of said transceivers, each respective clock-data recovery module including a respective fractionally adjustable frequency-lock loop; and
a reference clock input providing a reference clock for said plurality of fractionally adjustable phase-locked loops and said plurality of fractionally adjustable frequency-lock loops.
10. The integrated circuit device of claim 9 wherein:
input data having a data rate is input to each respective clock-data recovery module;
said respective frequency-lock loop of said respective clock-data recovery module locks to a rate close to said data rate; and
said respective clock-data recovery module further comprises a respective data-lock loop that locks to said data rate after said respective frequency-lock loop locks to said rate close to said data rate.
11. The integrated circuit device of claim 9 wherein:
said reference clock input is a sole reference clock input that provides a reference clock for said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops; and
said clocking arrangement further comprises a single reference clock conductor for conducting said reference clock from said single reference clock input to said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops.
12. The integrated circuit device of claim 9 wherein:
said reference clock input comprises a plurality of separate reference clock inputs, each of which provides a separate reference clock to a predetermined subset of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops; and
said clocking arrangement further comprises a reference clock bus including a respective separate reference clock conductor for conducting each of the separate reference clocks from a respective one of said separate reference clock inputs directly to said respective predetermined subset of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops.
13. The integrated circuit device of claim 12 wherein the predetermined subset of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises only adjustable phase-locked loops.
14. The integrated circuit device of claim 13 wherein the predetermined subset of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises said plurality of adjustable phase-locked loops.
15. The integrated circuit device of claim 12 wherein the predetermined subset of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises only adjustable frequency-lock loops.
16. The integrated circuit device of claim 15 wherein the predetermined subset of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises said plurality of adjustable frequency-lock loops.
17. The integrated circuit device of claim 9 , wherein said integrated circuit device is programmable.
18. The integrated circuit device of claim 17 , wherein said integrated circuit device is a programmable logic device.
19. A method of operating a programmable integrated circuit device having a plurality of transceivers, a plurality of fractionally adjustable phase-locked loops, and a respective clock-data recovery module in a receive portion of each respective one of said transceivers, each respective clock-data recovery module including a respective fractionally adjustable frequency-lock loop, and a reference clock conductor connected to said plurality of fractionally adjustable phase-locked loops and to each respective one of said plurality of fractionally adjustable frequency-lock loops, said method comprising:
applying a reference frequency signal to said reference clock conductor;
programming a respective transmit frequency for each respective one of a plurality of said transceivers;
programming a respective one of said plurality of fractionally adjustable phase-locked loops to output one said respective transmit frequency based on input of said reference frequency signal; and
programming each respective one of said plurality of fractionally adjustable frequency-lock loops to acquire a target received frequency based on input of said reference frequency signal.
20. The method of claim 19 wherein each respective clock-data recovery module further includes a respective data-lock loop, said method further comprising:
applying input data having a data rate to each respective clock-data recovery module, said target received frequency being close to said data rate; and
programming each respective data-lock loop to lock to said data rate after said respective frequency-lock loop locks to said target received frequency.
21. The method of claim 19 wherein:
said applying a reference frequency signal to said reference clock conductor comprises applying each of a plurality of separate reference clock inputs to one of a plurality of predetermined subsets of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops.
22. The method of claim 21 wherein one of the plurality of predetermined subsets of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises only adjustable phase-locked loops.
23. The method of claim 22 wherein the one of the plurality of predetermined subsets of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises said plurality of adjustable phase-locked loops.
24. The method of claim 21 wherein one of the plurality of predetermined subsets of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises only adjustable frequency-lock loops.
25. The method of claim 24 wherein the one of the plurality of predetermined subsets of said plurality of adjustable phase-locked loops and said plurality of adjustable frequency-lock loops comprises said plurality of adjustable frequency-lock loops.