Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool

1. An electric design automation (EDA) tool for generating a design of a system on a target device, comprising:

a graphical user interface to create a block based schematic;

a library unit that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data; and

a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.

2. The EDA tool of claim 1 , wherein the change made to the parameterizable filter block comprises changing an interpolation rate of the parameterizable filter block.

3. The EDA tool of claim 1 , wherein the change made to the parameterizable filter block comprises changing a decimation rate of the parameterizable filter block.

4. The EDA tool of claim 1 , wherein the change made to the parameterizable filter block comprises changing a number of channels supported by the parameterizable filter block.

5. The EDA tool of claim 1 , wherein the change made to the parameterizable filter block comprises changing a clock rate of the parameterizable filter block.

6. The EDA tool of claim 1 , wherein parameterizable filter block is a cascaded integrator-comb (CIC) filter.

7. The EDA tool of claim 1 , wherein the parameterizable filter block is a finite infinite response (FIR) filter.

8. The EDA tool of claim 1 , wherein the design adjustment unit modifies a selected wire to a new wire that supports a greater amount of data.

9. The EDA tool of claim 1 , wherein the design adjustment unit modifies a selected wire to a new wire that supports a lesser amount of data.

10. The EDA tool of claim 1 , wherein the design adjustment unit modifies a selected component by enabling the component to support processing of a greater amount of data.

11. The EDA tool of claim 1 , wherein the design adjustment unit modifies a selected component by enabling the component to support processing of a lesser amount of data.

12. The EDA tool of claim 1 , wherein the filter block supports a plurality of channels where a cumulative sample rate of the channels is greater than or equal to a clock rate of the system.

13. The EDA tool of claim 12 , further comprising an intermediate representation generator to generate an intermediate representation of the system from the functional units selected from the library, wherein for each parameterizable filter block, a sub-filter is assigned to each channel.

14. The EDA tool of claim 1 , further comprising an intermediate representation generator to generate an intermediate representation of the system from a description of the system that does not include any pipeline delays, the description of the system made up from functional units selected from the library.

15. The EDA tool of claim 1 , further comprising a high level synthesis unit to generate a register transfer language (RTL) representation of the system to be implemented on a target device specified by the designer from an intermediate representation of the system, the RTL representation including pipelined delays to allow the system to satisfy a maximum frequency of a clock as implemented on the target device.

16. A method for designing a system to be implemented on a target device, comprising:

providing a library of selectable functional units selectable by a designer to generate a block based schematic of a system to be implemented on a target device, the library of selectable functional units including a parameterizable filter block to represent a component in the design that filters data;

determining whether a change has been made to the parameterizable filter block by the designer, and

automatically modifying previously selected functional units and wires in the design without input from the designer upon determining the change, wherein one of the providing, determining, and modifying procedures is performed on a processor.

17. The method of claim 16 , wherein determining whether a change is made comprises determining whether an interpolation rate of the parameterizable filter block has been changed.

18. The method of claim 16 , wherein determining whether a change is made comprises determining whether a decimation rate of the parameterizable filter block has been changed.

19. The method of claim 16 , wherein determining whether a change is made comprises determining whether a number of channels supported by the parameterizable filter block has been changed.

20. The method of claim 16 , wherein determining whether a change is made comprises determining whether a clock rate of the parameterizable filter block has been changed.

21. The method of claim 16 , wherein modifying comprises changing a selected wire to a new wire that supports greater amount of data.

22. The method of claim 16 , wherein modifying comprises changing a selected component by enabling the component to support processing of a greater amount of data.

23. The method of claim 16 , further comprising generating an intermediate representation of the system from the functional units selected from the library, wherein for each parameterizable filter block, a sub-filter is assigned to each channel.

24. The method of claim 16 , further comprising generating an intermediate representation of the system from a description of the system that does not include any pipeline delays, the description of the system made up from functional units selected from the library.

25. A computer-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which when executed by a computer causes the machine to perform:

providing a library of selectable functional units selectable by a designer to generate a description of the system, the library of selectable functional units including a parameterizable filter block to represent a component in the design that filters data;

determining whether a change is made to the parameterizable filter block by the designer; and

automatically modifying previously selected functional units and wires in the design without input from the designer upon determining the change.

26. The computer-readable medium of claim 25 , further comprising instructions which when executed causes the computer to further perform generating an intermediate representation of the system from the functional units selected from the library, wherein for each parameterizable filter block, a sub-filter is assigned to each channel.

27. The computer-readable medium of claim 25 , further comprising instructions which when executed causes the computer to further perform generating an intermediate representation of the system from a description of the system that does not include any pipeline delays, the description of the system made up from functional units selected from the library.

28. An electric design automation (EDA) tool for generating a design of a system on a target device, comprising:

a library that includes a plurality of selectable functional units including a parameterizable filter block selectable by a designer to represent a component in the design that filters data, wherein the component supports a plurality of channels and a cumulative sample rate of the channels component is greater than or equal to a clock rate of the system.

29. The EDA tool of claim 28 , further comprising an intermediate representation generator to generate an intermediate representation of the system from the functional units selected from the library, wherein for each parameterizable filter block, a sub-filter is assigned to each channel.