Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry
View Patent ↗A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.
1. A programmable logic device comprising:
digital signal processing circuitry comprising at least one embedded multiplier of a particular size; and
programmable logic circuitry, wherein a user logic design multiplier of a size greater than the particular size is implemented by a user logic design to hardware application using the at least one embedded multiplier and the programmable logic circuitry.
2. The programmable logic device of claim 1 wherein the particular size is a largest size available among all embedded multipliers in the programmable logic device that is still smaller than the size of the user logic design multiplier.
3. The programmable logic device of claim 1 , wherein the user logic design multiplier is used to implement an infinite impulse response filter.
4. The programmable logic device of claim 1 , wherein the user logic design multiplier is used to implement an finite impulse response filter.
5. A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
6. The printed circuit board defined in claim 5 further comprising:
a memory mounted on the printed circuit board and coupled to the programmable logic device.
7. The printed circuit board defined in claim 5 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
8. The programmable logic device of claim 1 wherein:
the programmable logic circuitry is configured to implement at least one component multiplier; and
the at least one component multiplier and the at least one embedded multiplier generate partial products, the sum of which is the product of the user logic design multiplier.
9. The programmable logic device of claim 8 wherein the at least one component multiplier comprises three component multipliers implemented using programmable logic circuitry.
10. The programmable logic device of claim 8 wherein the at least one component multiplier comprises two component multipliers implemented using programmable logic circuitry.
11. The programmable logic device of claim 8 wherein:
the user logic design multiplier has a size that exceeds the particular size of the at least one embedded multiplier by one bit on one side of the at least one embedded multiplier; and
the at least one component multiplier comprises a single component multiplier implemented using programmable logic circuitry.
12. The programmable logic device of claim 8 further comprising circuitry for generating the sum of partial products of the at least one component multiplier and the at least one embedded multiplier.
13. The programmable logic device of claim 8 , further comprising bit shifting circuitry for shifting the output of one of the at least one component multiplier and the embedded multiplier.
14. The programmable logic device of claim 8 , further comprising bit padding circuitry for padding the output of one of the at least one component multiplier and the embedded multiplier.