On-die jitter generator

1. An integrated circuit (IC) comprising:

a jitter generator, wherein the jitter generator is integral with the IC and generates non-intrinsic jitter, wherein the jitter generator comprises:

a low frequency jitter generator (LFJG); and

a high frequency jitter generator (HFJG) coupled to the LFJG;

a multiplexer coupled to the LFJG and HFJG, wherein the multiplexer includes a first input terminal coupled to an output terminal of the LFJG, a second input terminal coupled to an output terminal of the HFJG, and a third input terminal coupled to a normal transmit data signal input.

2. The IC of claim 1 , wherein the non-intrinsic jitter is used to test jitter tolerance of the IC.

3. The IC of claim 1 further comprising:

a transmit driver coupled to the multiplexer;

wherein the multiplexer further includes an output terminal coupled to an input terminal of the transmit driver;

further wherein the multiplexer selects an input signal received on one of the first, second, and third input terminals and provides the input signal to the transmit driver.

4. The IC of claim 1 , wherein the IC is a programmable logic device.

5. A digital system comprising the IC of claim 1 .

6. An integrated circuit (IC) comprising:

a jitter generator comprising:

a low frequency jitter generator (LFJG);

a high frequency jitter generator (HFJG) coupled to the LFJG; and

a multiplexer coupled to the LFJG and HFJG, wherein the multiplexer includes a first input terminal coupled to an output terminal of the LFJG, a second input terminal coupled to an output terminal of the HFJG, and a third input terminal coupled to a normal transmit data signal input,

wherein the jitter generator is integrated with the IC and generates non-intrinsic jitter, wherein the non-intrinsic jitter is used to measure a characteristic of the IC.

7. The IC of claim 6 , wherein the non-intrinsic jitter is used to test jitter tolerance of the IC.

8. The IC of claim 6 further comprising:

a transmit driver coupled to the multiplexer;

wherein the multiplexer further includes an output terminal coupled to an input terminal of the transmit driver;

further wherein the multiplexer selects an input signal received on one of the first, second, and third input terminals and provides the input signal to the transmit driver.

9. The IC of claim 6 , wherein the IC is a programmable logic device.

10. A digital system comprising the IC of claim 6 .

11. An integrated circuit (IC) comprising:

a jitter generator comprising:

a low frequency jitter generator (LFJG), wherein the LFJG includes a first register and a delay modulator coupled to the first register;

a high frequency jitter generator (HFJG) coupled to the LFJG, wherein the HFJG includes a phase interpolator and a second register coupled to the phase interpolator and the first register;

a multiplexer coupled to the LFJG and HFJG, wherein the multiplexer includes a first input terminal coupled to an output terminal of the LFJG and a second input terminal coupled to an output terminal of the HFJG; and

a transmit driver coupled to the multiplexer, wherein an input terminal of the transmit driver is coupled to an output terminal of the multiplexer,

wherein the jitter generator is integrated with the IC and generates non-intrinsic jitter.

12. The IC of claim 11 , wherein jitter generated by the jitter generator is used to test jitter tolerance of the IC or another IC device coupled to the IC.

13. The IC of claim 11 , wherein the multiplexer further includes a third input terminal coupled to a normal transmit data signal input, further wherein the multiplexer selects between an input signal received on one of the first, second, and third input terminals and provides the input signal to the transmit driver.

14. The IC of claim 13 , wherein an output terminal of the delay modulator is coupled to the first input terminal of the multiplexer and an output terminal of the second register is coupled to the second input terminal of the multiplexer.

15. The IC of claim 11 , wherein the IC is a programmable logic device.

16. A digital system comprising the IC of claim 11 .

17. An integrated circuit (IC) comprising:

a jitter generator, wherein the jitter generator is integral with the IC and generates non-intrinsic jitter, wherein the jitter generator comprises:

a low frequency jitter generator (LFJG), wherein the LFJG includes a first register and a delay modulator coupled to the first register; and

a high frequency jitter generator (HFJG) coupled to the LFJG.

18. The IC of claim 17 , wherein the HFJG includes a phase interpolator and a second register coupled to the phase interpolator and the first register, the IC further comprising:

a multiplexer coupled to the LFJG and HFJG, wherein the multiplexer includes a first input terminal coupled to an output terminal of the LFJG and a second input terminal coupled to an output terminal of the HFJG, further wherein an output terminal of the delay modulator is coupled to the first input terminal of the multiplexer and an output terminal of the second register is coupled to the second input terminal of the multiplexer.

19. An integrated circuit (IC) comprising:

a jitter generator comprising:

a low frequency jitter generator (LFJG); and

a high frequency jitter generator (HFJG) coupled to the LFJG, wherein the HFJG includes a phase interpolator and a first register coupled to the phase interpolator,

wherein the jitter generator is integrated with the IC and generates non-intrinsic jitter, wherein the non-intrinsic jitter is used to measure a characteristic of the IC.

20. The IC of claim 19 , wherein the LFJG includes a second register and a delay modulator coupled to the second register, further wherein the first register is coupled to the second register, the IC further comprising:

a multiplexer coupled to the LFJG and HFJG, wherein the multiplexer includes a first input terminal coupled to an output terminal of the LFJG and a second input terminal coupled to an output terminal of the HFJG, further wherein an output terminal of the delay modulator is coupled to the first input terminal of the multiplexer and an output terminal of the first register is coupled to the second input terminal of the multiplexer.