Method and system for dynamic table line encoding
View Patent ↗Disclosed are systems, apparatus, and methods for encoding data transmitted in a data line. In various embodiments, a device may include a first input port operative to receive a first data value. In some embodiments, the device may further include a first memory device operative to look up a second data value based on the first data value, where the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and where the memory device is operative to be configured according to a plurality of line encoding schemes. In various embodiments, the device may further include a first output port operative to provide an output signal, where the output signal comprises one or more data values including the second data value.
1. A system comprising:
a first input for receiving a first data value;
a memory device for providing a second data value based on the first data value, wherein the second data value is a representation of the first value according to a first scheme; and
a first output for providing the second data value.
2. The system of claim 1 , wherein the second data value allows for clock recovery, and wherein the first scheme is a line encoding scheme.
3. The system of claim 1 , wherein the second data value is also based on an arithmetic operation associated with the first data value.
4. The system of claim 1 , wherein the memory device is further for providing a third data value based on the first data value, wherein the third data value is a representation of the first value according to a second scheme.
5. The system of claim 4 , further comprising:
a second output for providing the third data value.
6. The system of claim 5 , wherein the second output is adjacent to the first output.
7. The system of claim 1 , further comprising:
a processor for providing the first scheme to the memory device.
8. The system of claim 7 , wherein the processor is also for providing a second scheme to the memory device, the second scheme provided to the first memory based on a first error rate associated with the first scheme.
9. The system of claim 7 , wherein the processor is also for providing a second scheme and a third scheme to the memory device, wherein the first scheme is associated with a first error rate, the second scheme is associated with a second error rate, and the third scheme is associated with a third error rate, and wherein the processor is also for determining a lowest error rate among the first error rate, the second error rate, and the third error rate.
10. The system of claim 9 , wherein the first scheme is associated with a first scheme type, the second scheme is associated with a second scheme type, and the third scheme is associated with a third scheme type, the scheme types selected from the group consisting of: a positively biased scheme using more high bits than low bits, a negatively biased scheme using more low bits than high bits, and a neutral scheme using equal amounts of high bits and low bits.
11. A method comprising:
receiving a first data value at a first input port of a memory device;
identifying a second data value based on the first data value, wherein the second data value is a representation of the first value according to a first scheme in the memory device; and
providing the second data value at a first output port of the memory device.
12. The method of claim 11 , wherein the second data value allows for clock recovery, and wherein the first scheme is a line encoding scheme.
13. The method of claim 11 , wherein the second data value is also based on an arithmetic operation associated with the first data value.
14. The method of claim 11 , further comprising:
providing, at a second output port, a third data value based on the first data value, wherein the third data value is a representation of the first value according to a second scheme.
15. The method of claim 14 , wherein the second output port is adjacent to the first output port.
16. The method of claim 11 , further comprising:
receiving a second scheme, the second scheme provided to the memory device based on a first error rate associated with the first scheme.
17. The method of claim 11 , further comprising:
receiving a second scheme and a third scheme, wherein the first scheme is associated with a first error rate, the second scheme is associated with a second error rate, and the third scheme is associated with a third error rate; and
determining a lowest error rate among the first error rate, the second error rate, and the third error rate.
18. The method of claim 17 , wherein the first scheme is associated with a first scheme type, the second scheme is associated with a second scheme type, and the third scheme is associated with a third scheme type, the scheme types selected from the group consisting of: a positively biased scheme using more high bits than low bits, a negatively biased scheme using more low bits than high bits, and a neutral scheme using equal amounts of high bits and low bits.
19. A non-transitory computer readable medium having instructions stored thereon, the instructions executable by a device to:
receive a first data value at a first input port of the device;
identify a second data value based on the first data value, wherein the second data value is a representation of the first value according to a first scheme in the device; and
provide the second data value at a first output port of the device.
20. The non-transitory computer readable medium of claim 19 , wherein the instructions are further executable by the device to:
receive a second scheme and a third scheme, wherein the first scheme is associated with a first scheme type, the second scheme is associated with a second scheme type, and the third scheme is associated with a third scheme type, the scheme types selected from the group consisting of: a positively biased scheme using more high bits than low bits, a negatively biased scheme using more low bits than high bits, and a neutral scheme using equal amounts of high bits and low bits.
21. A method for providing a scheme to a memory device, the method comprising:
providing, by a computer system, a first scheme for providing a second data value based on a first data value;
receiving, on the computer system, the first data value associated with a first input port of a memory device; and
receiving, on the computer system, the second data value associated with a first output port of the memory device, wherein the second data value is a representation of the first data value according to the first scheme.
22. The method of claim 21 , further comprising:
providing, by the computer system, a second scheme and a third scheme, wherein the first scheme is associated with a first error rate, the second scheme is associated with a second error rate, and the third scheme is associated with a third error rate; and
determining, by the computer system, a lowest error rate among the first error rate, the second error rate, and the third error rate, and wherein the first scheme is associated with a first scheme type, the second scheme is associated with a second scheme type, and the third scheme is associated with a third scheme type, the scheme types selected from the group consisting of: a positively biased scheme using more high bits than low bits, a negatively biased scheme using more low bits than high bits, and a neutral scheme using equal amounts of high bits and low bits.