Programmable logic device with fine-grained disaggregation
A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
1. An integrated circuit device, comprising:
a first die, comprising:
a semiconductor substrate;
circuitry that is formed on the semiconductor substrate and that includes embedded functional blocks, wherein the embedded functional blocks form a majority of all circuitry on the semiconductor substrate, wherein the majority of all circuitry comprises at least 70% of all circuitry; and
transmission circuitry formed on the semiconductor substrate to:
receive digital signal processing address data and memory address data; and
transmit the digital signal processing address data and the memory address data; and
a second die having digital signal processing blocks, wherein at least two of the embedded functional blocks in the first die directly overlap with one of the digital signal processing blocks in the second die.
2. The integrated circuit device of claim 1 , wherein the embedded functional blocks comprise memory blocks.
3. The integrated circuit device of claim 1 , wherein the embedded functional blocks comprise random-access memory blocks.
4. The integrated circuit device of claim 3 , wherein the embedded functional blocks comprise digital signal processing blocks.
5. The integrated circuit device of claim 1 , wherein the embedded functional blocks comprise digital signal processing blocks.
6. The integrated circuit device of claim 1 , wherein the circuitry comprises a memory address decoding logic circuit.
7. The integrated circuit device of claim 1 , wherein the circuitry comprises a clocking logic circuit.
8. The integrated circuit device of claim 1 , wherein the circuitry comprises a calibration circuit or a debugging circuit.
9. A system, comprising:
a first die having configurable logic blocks, wherein the first die comprises transmission circuitry formed on the first die to:
receive digital signal processing address data and memory address data; and
transmit the digital signal processing address data and the memory address data; and
a second die having digital signal processing blocks, wherein at least two of the configurable logic blocks in the first die directly overlap with one of the digital signal processing blocks in the second die.
10. The system of claim 9 , wherein the first die is stacked on the second die.
11. The system of claim 9 , wherein the configurable logic blocks form a majority of all circuitry on the first die.
12. The system of claim 9 , wherein the second die does not include any configurable logic blocks.
13. The system of claim 9 , wherein the first die and the second die form a programmable device that is part of a selected one of: a datacenter, a computer networking system, a data networking system, a digital signal processing system, a graphics processing system, a video processing system, a computer vision processing system, a cellular base station, a virtual reality system, an augmented reality system, a network functions virtualization platform, an artificial neural network, and an autonomous driving system.
14. The system of claim 9 , wherein the configurable logic blocks comprise logic array blocks (LABs).
15. A system, comprising:
a first die having configurable logic blocks, wherein the first die comprises transmission circuitry formed on the first die to:
receive digital signal processing address data and memory address data; and
transmit the digital signal processing address data and the memory address data; and
a second die having digital signal processing blocks, wherein the first and second die are stacked with the first die on top of the second die, and wherein at least two of the configurable logic blocks in the first die directly overlap with one of the digital signal processing blocks in the second die when viewed from a top-down view of the stacked first and second die.
16. The system of claim 15 , wherein receiving the digital signal processing address data and the memory address data comprises receiving the digital signal processing address data and the memory address data from the second die.
17. The system of claim 16 , wherein transmitting the digital signal processing address data and memory address data comprises transmitting encoded digital signal processing address data and encoded memory address data to the second die.
18. The system of claim 15 , wherein the second die does not include any configurable logic blocks.
19. The system of claim 15 , wherein the first die and the second die form a programmable device that is part of a selected one of: a datacenter, a computer networking system, a data networking system, a digital signal processing system, a graphics processing system, a video processing system, a computer vision processing system, a cellular base station, a virtual reality system, an augmented reality system, a network functions virtualization platform, an artificial neural network, and an autonomous driving system.
20. The system of claim 15 , wherein the configurable logic blocks comprise logic array blocks (LABs).