Look-up table based memory

1. A method for selectively configuring a look-up table, comprising;

providing a write address decoder for each logic element within a logic array block;

interconnecting each logic element of the logic array block through a write bus providing column select and row select signals from the corresponding write address decoder;

selecting to operate the look up table as one of a combinational logic device or a memory element based on values of first and second selects signals; and

reading data from the look-up table based on the value of the first select signal.

2. The method of claim 1 , wherein the values are generated from a configuration.

3. A method for selectively configuring a look-up table, comprising;

providing a write address decoder for each logic element within a logic array block;

interconnecting each logic element of the logic array block through a write bus providing column select and row select signals from the corresponding write address decoder;

selecting to operate the look up table as one of a combinational logic device or a memory element based on values of first and second selects signals; and

multiplexing a data input into the look-up table based on a value of the first select signal.

4. The method of claim 1 , further comprising:

selecting a single bit from one of the look-up table or another look-up table as an output when operating the look-up table as the memory element.

5. The method of claim 1 , wherein multiplexers and drivers of the look-up table are shared for use as a read address decoder.

6. The method of claim 1 , further comprising:

selecting a single bit from the look-up table and another single bit from another look-up table as an output when operating the look-up table as the memory element.

7. The method of claim 1 , wherein the interconnecting comprises:

distributing output of the write address decoder among multiple remaining logic elements of the logic array block.

8. The method of claim 1 , further comprising:

reassigning an order associated with write addresses from the write address decoder based on a distance to the write address decoder.

9. An integrated circuit device having selectable memory elements, comprising;

a logic array block (LAB) disposed within the device, the LAB including,

a plurality of logic elements, the plurality of logic elements having look-up tables functioning as the selectable memory elements;

a data path that shares multiplexers and drivers when the look-up tables of the logic elements are operated as one of a memory element or a combinational logic device, wherein read decoding circuitry utilized when the logic elements are operated as a memory element controls data input when the logic elements are operated as a combinational logic device; and

a write address decoder included within each of the plurality of logic elements and interconnected with the plurality of logic elements.

10. The device of claim 9 , wherein the look-up tables are operated as memory elements based on a configuration bit stream of the device.

11. The device of claim 10 , wherein an output of the memory elements has one of a two bit data width or a single bit data width.

12. The device of claim 9 , wherein a number of input signals to each of the logic elements remains constant whether operating the look-up tables as one of the memory element or the combinational logic device.

13. An integrated circuit device having selectable memory elements, comprising:

a logic array block (LAB) disposed within the device, the LAB including,

a plurality of logic elements, the plurality of logic elements having look-up tables functioning as the selectable memory elements;

a data path that shares multiplexers and drivers when the look-up tables of the logic elements are operated as one of a memory element or a combinational logic device:

a first multiplexer multiplexing in a data value for use when operating the look-up tables as the memory element; and

a write address decoder included within each of the plurality of logic elements and interconnected with the plurality of logic elements.

14. The device of claim 13 , further comprising:

a second multiplexer configured to provide a read address when operating the look-up tables as the memory element, wherein the first multiplexer and the second multiplexer share a select signal.

15. The device of claim 14 , further comprising:

a single output multiplexer receiving output from two look-up tables, the single output multiplexer receiving output of the second multiplexer as a select signal.

16. The device of claim 9 , further comprising:

output multiplexers receiving output from corresponding look-up tables, wherein each of the output multiplexers receives respective select signals from output of corresponding multiplexers.

17. The device of claim 16 , wherein the output multiplexers are cross coupled with regard to respective inputs.

18. The device of claim 9 , wherein the device comprises a programmable logic device (PLD).

19. A logic element, comprising:

a first and second look-up table, the first and the second look-up table selectively functioning as one of a combinational logic device or a memory element based on bit values of a configuration bit stream;

a write address decoder module dedicated to the logic element, the write address decoder module in communication with the first and the second look-up table through a bit line control module of the logic element, and

read address decoding circuitry including a first multiplexer outputting a select signal to a second multiplexer, wherein the read address decoding circuitry controls data input to the first and second look-up table when functioning as the combinational logic device.

20. The logic element of claim 19 , wherein the write address decoder module receives input from a write address line and provides output to a column and row select line that is in communication with the bit line control module.

21. The logic element of claim 19 , wherein the second multiplexer receives output from the first look-up table.

22. The logic element of claim 21 , wherein the

first multiplexer receives having one of the bit values as a select signal.

23. A logic element, comprising:

a first and second look-up table, the first and the second look-up table selectively functioning as one of a combinational logic device or a memory element based on bit values of a configuration bit stream,

a write address decoder module dedicated to the logic element, the write address decoder module in communication with the first and the second look-up table through a bit line control module of the logic element; and

read address decoding circuitry including a multiplexer having one of the bit values as a select signal, wherein the one of the bit values is shared with another multiplexer providing a data input path into the logic element.

24. The logic element of claim 22 , wherein the second multiplexer receives one of the bit values from the configuration bit stream as a select signal.