Electronic assembly apparatus and associated methods
View Patent ↗A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.
1. A method of fabricating an electronic assembly, the method comprising:
fabricating, using a photolithography process, a first interconnect comprising a first set of copper pillars, the first interconnect to interconnect a first die to a semiconductor substrate;
fabricating, using the photolithography process, a second interconnect comprising a second set of copper pillars, the second interconnect to interconnect the first die to a second die; and
assembling the first die, the second die, and the semiconductor substrate together such that the first die is disposed above the semiconductor substrate, and the second die is disposed below the first die.
2. The method according to claim 1 , wherein fabricating the first and second interconnects further comprises fabricating the first and second sets of copper pillars such that the first set of copper pillars are taller than the second set of copper pillars.
3. The method according to claim 2 , wherein fabricating the first interconnect further comprises fabricating the first set of copper pillars on the first die.
4. The method according to claim 3 , wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the first die.
5. The method according to claim 3 , wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the second die.
6. The method according to claim 1 , wherein fabricating the first interconnect further comprises fabricating the first set of copper pillars on the semiconductor substrate.
7. The method according to claim 6 , wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the first die.
8. The method according to claim 6 , wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the second die.
9. The method according to claim 1 , wherein fabricating the second interconnect further comprises coupling analog circuitry fabricated in one of the first and second die to digital circuitry fabricated in the other of the first and second die.
10. The method according to claim 1 , wherein fabricating the second interconnect further comprises coupling analog or mixed-signal circuitry fabricated in one of the first and second die to digital circuitry fabricated in the other of the first and second die.
11. The method according to claim 1 , wherein fabricating the second interconnect further comprises coupling field programmable gate array (FPGA) circuitry fabricated in one of the first and second die to circuitry fabricated in the other of the first and second die.
12. A method of fabricating an electronic assembly, the method comprising:
fabricating a first interconnect, the first interconnect to interconnect a first die to a substrate;
fabricating a second interconnect, the second interconnect to interconnect the first die to a second die;
fabricating a third interconnect, the third interconnect to interconnect the first die to a third die; and
assembling the first die, the second die, the third die, and the substrate together such that the first die is disposed above the substrate, the second die is disposed below the first die, and the third die is disposed below the first die,
wherein assembling the first die, the second die, the third die, and the substrate together further comprises disposing the second die between the first die and the third die.
13. The method according to claim 11 , wherein fabricating the first interconnect further comprises fabricating a first set of copper pillars, wherein fabricating the second interconnect further comprises fabricating a second set of copper pillars, and wherein fabricating the third interconnect further comprises fabricating a third set of copper pillars.
14. The method according to claim 13 , wherein the first set of copper pillars are taller than the second set of copper pillars.
15. The method according to claim 14 , wherein the second set of copper pillars are taller than the third set of copper pillars.
16. A method of fabricating an electronic assembly, the method comprising:
fabricating, using a photolithography process, a first interconnect on a first die, the first interconnect comprising a first set of copper pillars;
fabricating, using a photolithography process, a second interconnect on the first die, the second interconnect comprising a second set of copper pillars;
interconnecting a second die to the first die using the second interconnect; and
interconnecting the first die to a semiconductor substrate using the first interconnect such that the first die and the second die are disposed above the substrate.
17. The method according to claim 16 , wherein interconnecting a second die to the first die using the second interconnect further comprises disposing the second die above the first die.
18. The method according to claim 17 , wherein interconnecting the first die to a substrate using the first interconnect such that the first die and the second die are disposed above the substrate further comprises using a flip chip technique.
19. The method according to claim 16 , wherein fabricating the first and second interconnects on the first die further comprises:
fabricating a first photoresist layer;
etching selectively the first photoresist layer to fabricate first and second sets of openings; and
depositing copper in the first and second sets of openings.
20. The method according to claim 19 , wherein fabricating the first and second interconnects on the first die further comprises performing a first planarization step.
21. The method according to claim 19 , wherein fabricating the first and second interconnects on the first die further comprises:
fabricating a second photoresist layer;
etching selectively the second photoresist layer to fabricate a third set of openings; and
depositing copper in the third set of openings.
22. The method according to claim 21 , wherein fabricating the first and second interconnects on the first die further comprises performing a second planarization step.
23. The method according to claim 21 , wherein fabricating the first and second interconnects on the first die further comprises etching the first and second photoresist layers.