Pipelined direct drive routing fabric
View Patent ↗One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.
1. A method for pipelined direct-drive routing in a programmable logic device, the method comprising:
programming a mode multiplexer to a pipeline mode, the mode multiplexer comprising a first tri-state buffer, and the mode multiplexer having first and second inputs and an output;
selecting the signal by a routing multiplexer, the routing multiplexer having multiple inputs and an output, wherein the output of the routing multiplexer is connected to the first input of the mode multiplexer;
outputting the signal from the output of the routing multiplexer to an input of a flip-flop;
delaying the signal by the flip-flop;
outputting the signal from an output of the flip-flop to a second input of the mode multiplexer; and
outputting the signal from the mode multiplexer to a driver circuit.
2. The method of claim 1 , wherein said delaying depends on a clock signal received at a clock input of the flip-flop.
3. The method of claim 1 , wherein the flip-flop is a member of a common pool of flip-flops that is shared by a plurality of routing multiplexers.
4. The method of claim 1 , wherein the routing multiplexer comprises a driver input multiplexer in a routing fabric of the programmable logic device, and the output line comprises a routing wire.
5. The method of claim 1 , wherein the routing multiplexer comprises a logic-array-block (LAB) input multiplexer in a routing fabric of the programmable logic device, and the output line comprises a LAB line.
6. The method of claim 1 , wherein the mode multiplexer further comprises a second tri-state buffer.
7. The method of claim 6 , further comprising:
driving an output line using the driver circuit, wherein the outputs of the first and second tri-state buffers are connected to the input of the driver circuit.
8. The method of claim 1 , wherein the routing multiplexer comprises a driver input multiplexer in a routing fabric of the programmable logic device, and the output line comprises a routing wire.
9. The method of claim 1 , wherein the routing multiplexer comprises a logic-array-block (LAB) input multiplexer in a routing fabric of the programmable logic device, and the output line comprises a LAB line.
10. The method of claim 1 , wherein the output of the routing multiplexer is directly connected to the input of the flip-flop.
11. A circuit for pipelined direct-drive routing in a programmable logic device, the circuit comprising:
a routing multiplexer having multiple inputs and an output;
a first tri-state buffer having an input and an output, wherein the input of the first tri-state buffer is connected to the output of the routing multiplexer at a storage node of the circuit;
a second tri-state buffer having an input and an output, wherein the input of the second tri-state buffer is connected to the storage node; and
a feed forward inverter having an input and an output, wherein the input of the feed forward inverter is connected to the storage node and the output of the feed-forward inverter is connected to the output of the second tri-state buffer.
12. The circuit of claim 11 , further comprising:
a programmable latch control circuit which receives a pulse signal and, if programmed in a pipeline mode, asserts a latch enable pulse to the first tri-state buffer.
13. The circuit of claim 11 , further comprising:
a driver circuit having an input and an output, wherein the input of the driver circuit is connected to the storage node.
14. The circuit of claim 11 , wherein the routing multiplexer comprises a driver input multiplexer in a routing fabric of the programmable logic device, and the output line comprises a routing wire.
15. The circuit of claim 11 , wherein the routing multiplexer comprises a logic-array-block (LAB) input multiplexer in a routing fabric of the programmable logic device, and the output line comprises a LAB line.