Programmable logic device with serial interconnect
View Patent ↗In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.
1. A programmable logic device comprising:
groupings of programmable logic resources;
programmable input/output resources; and
programmable interconnect resources for conveying signals among said groupings of programmable logic resources and between said programmable logic resources and said programmable input/output resources; wherein:
each of at least two portions of said programmable logic device comprises a serial interface;
said programmable interconnect resources comprise at least one serial interconnect between said serial interfaces of said at least two portions of said programmable logic device; and
each one of said serial interfaces operates synchronously with each other one of said serial interfaces over said at least one serial interconnect.
2. The programmable logic device of claim 1 wherein at least one of said two portions comprises one of said groupings of programmable logic resources.
3. The programmable logic device of claim 1 wherein at least one of said two portions comprises one of said programmable input/output resources.
4. The programmable logic device of claim 1 wherein at least one of said two portions comprises a portion of said programmable interconnect resources.
5. The programmable logic device of claim 1 wherein each of said portions comprises one said serial interface.
6. The programmable logic device of claim 5 wherein each said serial interface comprises a phase-locked loop.
7. The programmable logic device of claim 6 wherein said phase-locked loop is a digital phase-locked loop.
8. The programmable logic device of claim 1 comprising a common clock source for said serial interfaces.
9. The programmable logic device of claim 8 further comprising a clock tree for distributing said common clock source to said serial interfaces.
10. The programmable logic device of claim 8 wherein said common clock source is onboard said programmable logic device.
11. A digital processing system comprising:
processing circuitry;
a memory coupled to said processing circuitry; and
a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
12. A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
13. The printed circuit board defined in claim 12 further comprising:
memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.
14. The printed circuit board defined in claim 13 further comprising:
processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.
15. A method of configuring a programmable logic device, said programmable logic device having groupings of programmable logic resources, programmable input/output resources, and programmable interconnect resources for conveying signals among said groupings of programmable logic resources and between said programmable logic resources and said programmable input/output resources, said programmable interconnect resources comprise at least one serial interconnect between at least two portions of said programmable logic device, said method comprising:
on power-up of said programmable logic device, loading configuration data to implement a user configuration, including programming said programmable interconnect resources to use at least one of said at least one serial interconnect for synchronous serial communication between said at least two portions; and
after said loading, training, for said synchronous serial communication, each said at least one of said at least one serial interconnect used by said user configuration.
16. The method of claim 15 further comprising entering user mode after said training.
17. An integrated circuit device comprising:
groupings of circuits;
input/output resources; and
programmable interconnect resources for conveying signals among said groupings of circuits and between said groupings of circuits and said input/output resources; wherein:
each of at least two portions of said integrated circuit device comprises a serial interface;
said programmable interconnect resources comprise at least one serial interconnect between said serial interfaces of said at least two portions of said integrated circuit device; and
each one of said serial interfaces operates synchronously with each other one of said serial interfaces over said at least one serial interconnect.
18. The integrated circuit device of claim 17 , wherein said integrated circuit device comprises a programmable logic device.
19. A programmable logic device comprising:
programmable interconnect resources and serial interfaces; wherein:
said programmable interconnect resources comprise at least one serial interconnect between said serial interfaces; and
each one of said serial interfaces operates synchronously with each other one of said serial interfaces over said at least one serial interconnect.