Methods and apparatus for debugging a system with a hung data bus
View Patent ↗Methods and apparatus are provided to facilitate debugging of a system with a hung data bus. A register scan chain is used to read data from logic blocks of the hung system. The scan chain is also used to write data into the logic blocks, possibly resetting a subset of those blocks or otherwise causing them to exit the hung state. The resetting may terminate the hung instruction in a manner that allows subsequent instructions to be executed, including entry into debug mode.
1. Circuitry for forcing an integrated circuit out of a hung state, comprising:
at least one logic block implemented on the integrated circuit; and
at least one shift register circuit implemented on the integrated circuit, associated with the at least one logic block, wherein:
the at least one shift register circuit can write control data to the at least one logic block; and
each of the at least one logic block can reset itself responsive to the value of the control data.
2. The circuitry of claim 1 , further wherein:
the at least one shift register circuit can read status data from the at least one logic block.
3. The circuitry of claim 2 , wherein:
the status data comprises memory address data.
4. The circuitry of claim 2 , wherein:
the status data comprises data indicating a status of at least one first-in-first-out (“FIFO”) queue.
5. The circuitry of claim 2 , wherein:
the status data comprises data indicating a status of at least one internal signal within the at least one logic block.
6. The circuitry of claim 1 , wherein:
each of the at least one logic block is configured to reset itself responsive to a value of 1 in the control data.
7. The circuitry of claim 1 , wherein:
each of the at least one block is configured to release itself from a hung state responsive to a value of 1 in the control data.
8. The circuitry of claim 1 , wherein:
the at least one logic block comprises a microprocessor and bridge circuitry.
9. The circuitry of claim 8 , wherein:
resetting at least part of the bridge circuitry can release the microprocessor from a hung state.
10. The circuitry of claim 9 , wherein:
the hung state results from an unterminated read request issued from the microprocessor through the bridge circuitry.
11. The circuitry of claim 1 , further comprising:
JTAG logic circuitry connected to the at least one shift register circuit.
12. The circuitry of claim 11 , wherein:
the JTAG logic circuitry can provide the control data for the at least one shift register circuit.
13. The circuitry of claim 12 , wherein:
the JTAG logic circuitry can accept the status data from the at least one shift register circuit.
14. The circuitry of claim 11 , further comprising:
a JTAG cable connected to the JTAG logic circuitry; and
a host computer connected to the JTAG cable.
15. An integrated circuit, comprising the circuitry of claim 1 .
16. The integrated circuit of claim 15 , wherein the integrated circuit comprises:
an ASIC portion; and
a PLD portion.
17. A printed circuit board, comprising the integrated circuit of claim 15 .
18. A data processing system, comprising the printed circuit board of claim 16 .
19. A method of forcing an integrated circuit out of a hung state, comprising:
reading status data from at least one logic block implemented on the integrated circuit to at least one shift register implemented on the integrated circuit;
shifting the status data out of the at least one shift register;
shifting control data into the at least one shift register; and
writing the control data from the at least one shift register to the at least one logic block.
20. The method of claim 19 , wherein:
the writing is capable of resetting each of the at least one logic block, responsive to the control data.
21. The method of claim 20 , wherein:
resetting the at least one logic block can terminate a read instruction.
22. The method of claim 19 , wherein:
the shifting the status data and the shifting the control data occur simultaneously.
23. The method of claim 19 , wherein:
the status data is processed by JTAG logic circuitry; and
the control data is transferred from JTAG logic circuitry.
24. The method of claim 19 , further comprising:
resetting the at least one logic block to release the integrated circuit from a hung state; and
executing an instruction to enter debug mode.
25. Circuitry for reading status data from an integrated circuit and writing control data to the integrated circuit, comprising:
means for reading the status data from at least one logic block implemented on the integrated circuit; and
means for writing the control data from at least one shift register implemented on the integrated circuit to the at least one logic block, wherein:
the reading and writing can be performed while the integrated circuit is in a hung state; and
the writing can release the integrated circuit from the hung state.
26. The circuitry of claim 25 , wherein the at least one logic block comprises:
a microprocessor; and
a peripheral connected to the microprocessor.
27. The circuitry of claim 26 , wherein:
the integrated circuit enters the hung state after processing a read request from the microprocessor to the peripheral.
28. The circuitry of claim 25 , further comprising:
means for controlling the reading and writing using a JTAG protocol; and
means for entering a JTAG debug mode after releasing the integrated circuit from the hung state.