Method and system for operating a communication circuit during a low-power state
View Patent ↗A method and system for operating a communication circuit during periods of reduced energy consumption are disclosed. Data may be transmitted over a communication link from a first device to a second device in a low-power state. The data may be used by the second device to update coefficients and/or synchronize the receiver of the second device to a transmitter of the first device, thereby enabling a more efficient or rapid transition from the low-power state to an active state. A transmitter of the first device and a receiver of the second device may be activated before transmission of the data and deactivated after transmission of the data. In this manner, a receiver of the second device may be refreshed to enable a more efficient transition from the low-power state to an active state.
1. A method of operating a communication circuit, said method comprising:
activating, in a low-power state, a transmitter of a first device in response to an internally generated signal while allowing at least one other component of said first device to remain deactivated;
accessing data operable to refresh a receiver of a second device;
transmitting an alert signal to said second device to activate said receiver of said second device while enabling at least one other component of said second device to remain deactivated;
transmitting from said transmitter to said receiver of said second device over a communication link, said data operable to refresh said receiver of said second device; and
deactivating said transmitter of said first device.
2. The method of claim 1 , wherein said first device is a programmable logic device.
3. The method of claim 1 , wherein said communication link is an Ethernet link.
4. The method of claim 1 , wherein said data comprises a training frame, and wherein said training frame comprises information selected from a group consisting of a frame marker, data for updating communication coefficients, a status report, and a training pattern.
5. The method of claim 4 , wherein said training pattern enables synchronization of a first clock signal of said second device to a second clock signal of said first device.
6. The method of claim 1 further comprising:
accessing said data from a memory of said first device, and
wherein said data comprises communication coefficients that are derived from a coefficient negotiation phase between said first and second devices.
7. The method of claim 1 , wherein said transmitter is implemented within a physical medium attachment sublayer of said first device, and wherein said receiver is implemented within a physical medium attachment sublayer of said second device.
8. The method of claim 1 further comprising:
transitioning said first device from an active state to said low-power state; and
transitioning said first device from said low-power state to said active state.
9. The method of claim 8 , wherein said transitioning said first device from said active state to said low-power state further comprises:
accessing, at said first device, a request to transition to said low-power state;
encoding, at said first device, a symbol in data, wherein said symbol is associated with said request; and
transmitting said data comprising said symbol from said first device to said second device to initiate a transition of said first and second devices to said low-power state.
10. The method of claim 8 , wherein said transitioning said first device from said low-power state to said active state further comprises:
responsive to an event, activating a transmitter of said first device;
transmitting, over said communication link, an alert signal for reception by said second device;
bypassing a scrambler of said first device to accelerate block lock at said second device; and
reactivating at least one component of said first device to transition from said low-power state to an active state.
11. A protocol training component of a first device, said protocol training component comprising:
a memory operable to store data for refreshing a receiver of a second device during a low-power state; and
a controller coupled to said memory and operable, in said low-power state, to periodically:
activate a transmitter of said first device in response to an internally generated signal while allowing at least one other component of said first device to remain deactivated;
access said data for refreshing said receiver of said second device;
transmit an alert signal to said second device to activate said receiver of said second device while enabling at least one other component of said second device to remain deactivated;
transmit, over a communication link, said data from said transmitter to said receiver of said second device, wherein said data is further operable to enable an efficient transition from said low-power state to an active state; and
deactivate said transmitter of said first device.
12. The protocol training component of claim 11 , wherein said first device is a programmable logic device.
13. The protocol training component of claim 11 , wherein said data comprises a training frame, and wherein said training frame comprises information selected from a group consisting of a frame marker, data for updating communication coefficients, a status report, and a training pattern.
14. The protocol training component of claim 13 , wherein said training pattern enables synchronization of a first clock signal of said second device to a second clock signal of said first device.
15. The protocol training component of claim 11 , wherein said controller is further operable to access said data from said memory.
16. The protocol training component of claim 11 , wherein said transmitter is implemented within a physical medium attachment sublayer of said first device, and wherein said receiver is implemented within a physical medium attachment sublayer of said second device.
17. An integrated circuit comprising:
a transmitter; and
a memory operable to store data for refreshing a receiver of another device; and
a controller coupled to said memory and operable, in a low-power state, to periodically:
activate said transmitter in response to an internally generated signal while allowing at least one other component of said integrated circuit to remain deactivated;
access said data for refreshing said receiver of said another device;
transmit an alert signal to said another device to activate said receiver of said another device while enabling at least one other component of said another device to remain deactivated;
transmit, over a communication link, said data from said transmitter to said receiver of said another device, wherein said data is further operable to enable an efficient transition from said low-power state to an active state; and
deactivate said transmitter.
18. The integrated circuit of claim 17 , wherein said communication link is an Ethernet link.
19. The integrated circuit of claim 17 , wherein said data comprises a training frame, and wherein said training frame comprises information selected from a group consisting of a frame marker, data for updating communication coefficients, a status report, and a training pattern.
20. The integrated circuit of claim 19 , wherein said training pattern enables synchronization of a first clock signal of said another device to a second clock signal of a programmable logic device comprising said transmitter.
21. The integrated circuit of claim 17 , wherein said controller is further operable to access said data from said memory.
22. The integrated circuit of claim 17 further comprising:
a physical medium attachment sublayer, and
wherein said transmitter is implemented within said physical medium attachment sublayer, and wherein said receiver is implemented within a physical medium attachment sublayer of said another device.