Configuration context switcher with a clocked storage element
View Patent ↗Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
1. An integrated circuit (“IC”) comprising:
a configurable circuit for configurably performing one of a plurality of operations based on configuration data;
a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit;
an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different configuration data sets, said interconnect circuit comprising a set of clocked storage elements for temporarily storing the received configuration data sets, wherein the set of clocked storage elements is controlled by a pair of complementary clock signals.
2. The IC of claim 1 , wherein the pair of complementary clock signals comprises a first clock signal and a second clock signal, wherein the set of clocked storage elements store a set of configuration data when the first clock signal is at a high voltage and the second clock signal is at a low voltage.
3. The IC of claim 2 , wherein the set of clocked storage elements hold a previously stored set of configuration data when the first clock signal is at the low voltage and the second clock signal is at the high voltage.
4. The IC of claim 2 , wherein the pair of complementary clock signals have opposite polarities.
5. The IC of claim 2 , wherein the first clock signal drives n-type transistors in the set of clocked storage elements and the second clock signal drives p-type transistors in the set of clocked storage elements.
6. The IC of claim 2 , wherein both the first and second clock signals drives n-type transistors in the set of clocked storage elements.
7. The IC of claim 1 , wherein the pair of complementary clock signals comprises a first clock signal and a second clock signal, wherein when the first clock signal is for enabling the set of clocked storage elements to receive a set of configuration data and the second clock signal is for reinforcing stored logic values.
8. The IC of claim 2 , wherein the first clock signal swings between a mid-point voltage to the high voltage and the second clock signal swings between the mid-point voltage to the low voltage.
9. The IC of claim 8 , wherein the set of clocked storage elements output a previously stored set of configuration data when the first and second clock signals are at the mid-point voltage.
10. The IC of claim 8 , wherein the pair of complementary clock signals drives a transmission gate, wherein the first clock signal drives a n-type transistor in the transmission gate and the second clock signal drives a p-type transistor in the transmission gate.
11. An integrated circuit (“IC”) comprising:
a configurable circuit for configurably performing one of a plurality of operations based on configuration data;
a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit;
an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits in the plurality of storage circuits to receive different configuration data sets, said interconnect circuit comprising a clocked storage circuit for temporarily storing configuration data, wherein the clocked storage circuit receives a clock signal that enables the clocked storage circuit to store and receive configuration data, the clock signal having a first state and a second state, wherein (i) during the first state, the clock signal enables the clocked storage circuit to store a configuration data set received from the plurality of storage circuits and (ii) during the second state, the clock signal enables the clocked storage circuit to reinforce a logic value in the stored configuration data set.
12. The IC of claim 11 , wherein the clocked storage circuit comprises a pull-down transistor for reinforcing the logic value when the clock signal is at the second state.
13. The IC of claim 11 , wherein the clocked storage circuit comprises a pair of pull-up transistors.
14. The IC of claim 13 , wherein the pair of pull-up transistors are controlled by a pair of complimentary bit-lines from the plurality of storage circuits.
15. The IC of claim 13 , wherein the pair of pull-up transistors are controlled by the clock signal.
16. An electronic device comprising:
a memory device; and
an integrated circuit (“IC”) comprising:
a configurable circuit for configurably performing one of a plurality of operations based on configuration data provided by the memory device;
a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit; and
an interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different configuration data sets, said interconnect circuit comprising a set of clocked storage elements for temporarily storing the received configuration data sets, wherein the set of clocked storage elements is controlled by a pair of complementary clock signals.
17. The electronic device of claim 16 , wherein the pair of complementary clock signals comprises a first clock signal and a second clock signal, wherein the set of clocked storage elements stores a set of configuration data when the first clock signal is at a high voltage and the second clock signal is at a low voltage.
18. The electronic device of claim 17 , wherein the set of clocked storage elements holds a previously stored set of configuration data when the first clock signal is at the low voltage and the second clock signal is at the high voltage.
19. The electronic device of claim 17 , wherein the pair of complementary clock signals have opposite polarities.
20. The electronic device of claim 16 , wherein the pair of complementary clock signals comprises a first clock signal and a second clock signal, wherein when the first clock signal is for enabling the set of clocked storage elements to receive a set of configuration data and the second clock signal is for reinforcing stored logic values.