Method and apparatus for performing profile guided optimization for high-level synthesis

1. A method for designing a system on a target device, comprising:

performing a high-level compilation of a computer program language description of the system to generate a hardware description language (HDL) of the system, wherein the high-level compilation adds a description of hardware that collects profile data, to be implemented by the target device, to the HDL of the system, wherein the profile data comprises a number of threads which execute an identified block of logic in the system over a period of time, wherein the profile data further comprises operating parameters of a load store unit implemented in the system that comprises an instruction that reads or writes a value from an address in memory, and wherein performing the high-level compilation further comprises tracking values that reflect maximum and minimum address values accessed by the load store unit using first and second counters; and

generating a data file from the HDL of the system including the added description of the hardware that collects the profile data; and

programming the target device with the data file to physically transform components on the target device to implement the system.

2. The method of claim 1 , wherein the profile data comprises hardware profile data of the system implemented on the target device from an earlier HDL compilation of the system.

3. The method of claim 1 , wherein the profile data comprises hardware profile data of the system obtained by performing a simulation of an earlier HDL compilation of the system.

4. The method of claim 1 , wherein the profile data comprises report files generated by an earlier HDL compilation of the system.

5. The method of claim 1 , wherein the profile data comprises minimum and maximum latency values associated with variable latency instructions executed by the system.

6. The method of claim 1 , wherein the profile data comprises a number of threads enabled for predicated instructions executed by the system over a period of time.

7. The method of claim 1 , wherein the profile data comprises an indication of whether instructions enter a barrier in order.

8. The method of claim 1 , wherein the profile data comprises a value as to a number of threads executed by the system over a period of time.

9. The method of claim 1 , wherein the profile data comprises an area on the target device required to implement the system.

10. The method of claim 1 , wherein the profile data comprises a worst slack value for the system.

11. The method of claim 1 further comprising:

presenting optimization options and costs and benefits associated with the optimization options on a graphical user interface; and

performing an optimization option responsive to a user selecting the optimization option.

12. The method of claim 1 , wherein the description of the hardware added is implemented on the target device.

13. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method, comprising:

performing a high-level compilation of a computer program language description of a system to generate a hardware description language (HDL) of the system, wherein the high-level compilation adds a description of hardware for collecting hardware profile data, to be implemented by a target device, used for future high-level compilation of the system to the HDL of the system, wherein the hardware profile data comprises operating parameters of a load store unit that comprises an instruction that reads or writes a value from an address in memory, wherein performing the high-level compilation further comprises tracking a value that reflects a number of cycles that the load store unit is active using a first counter, tracking a value that reflects a number of cycles that the load store unit is idle using a second counter, and tracking a value that reflects a number of cycles that the load store unit is stalled using a third counter;

generating a data file from the HDL of the system including the added description of the hardware that collects the hardware profile data;

programming a target device with the data file to physically transform components on the target device to implement the system;

uploading the hardware profile data from the target device implementing the system; and

performing a second high-level compilation of the computer program language description of the system to generate a second hardware description language (HDL) of the system, wherein the second high-level compilation performs optimizations in response to the hardware profile data, wherein the optimizations comprises relaxing timing constraint for signals associated with a block of logic identified as not being used from the hardware profile data.

14. The non-transitory computer readable medium of claim 13 , wherein the method further comprises:

compiling the HDL to generate a programming file to program a target device to implement the system; and

generating report files from timing analysis of the compiled HDL.

15. The non-transitory computer readable medium of claim 13 , wherein the optimizations comprise removing hardware associated with an unused block of logic in response to information provided from the hardware profile data.

16. The non-transitory computer readable medium of claim 13 , wherein the high-level compilation is performed prior to HDL compilation of the system.

17. The non-transitory computer readable medium of claim 13 , wherein the description of the hardware added is implemented on the target device.

18. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system, comprising:

performing high-level compilation of a computer program language description of the system to generate a hardware description language (HDL) of the system, wherein performing the high-level compilation comprises adding a description of hardware for collecting hardware profile data, to be implemented on a target device, used for future high-level compilation of the system to the HDL of the system, wherein the hardware profile data comprises operating parameters of a load store unit that comprises an instruction that reads or writes a value from an address in memory, and wherein performing the high-level compilation further comprises tracking values that reflect maximum and minimum address values accessed by the load store unit using first and second counters;

presenting a plurality of optimization options and costs and benefits associated with the optimization options on a graphical user interface, wherein an optimization option is performed responsive to a user selecting the optimization option, during a second high-level compilation of the computer program language description of the system to generate a second HDL of the system;

generating a data file that describes the system that has been optimized according to the optimization option; and

programming a target device with the data file to physically transform components on the target device to implement the system.

19. The non-transitory computer readable medium of claim 18 further comprising:

synthesizing a logic design of the system from the HDL of the system;

placing the system on a target device;

routing the system on the target device; and

evaluating the system on the target device and generating report files describing slack on a critical path.

20. The non-transitory computer readable medium of claim 19 , wherein performing high-level compilation comprises performing the second high-level compilation of the computer program language description of the system to generate the second hardware description language (HDL) of the system, wherein the second high-level compilation performs optimizations in response to the hardware profile data and the report files.

21. The non-transitory computer readable medium of claim 18 , wherein the second high-level compilation performs optimizations in response to the hardware profile data collected from hardware added during the high-level compilation.