Run-time recovery of malformed interconnect response
View Patent ↗Various embodiments of the present disclosure provide techniques for monitoring one or more transactions output from a configurable logic system (CLS) to a hard logic system. The CLS and the hard logic system are communicatively coupled by a bridge. The hard logic system receives an exception indicating that a malformed interconnect response has been output by the CLS, clears all pending CLS transactions, isolating the CLS, and executes a run-time recovery process. The run-time recovery process may include reading an interconnect register to obtain an offending address, within the CLS, associated with the malformed interconnect response, and logging the offending address into a system log.
1. A method comprising:
monitoring one or more transactions output from a configurable logic system (CLS) to a hard logic system, the CLS and the hard logic system being communicatively coupled by a bridge; and, with the hard logic system:
receiving an exception, the exception indicating that a malformed interconnect response has been output by the CLS;
clearing all pending CLS transactions;
isolating the CLS; and
executing a run-time recovery process.
2. The method of claim 1 , wherein receiving the exception comprises receiving the exception at an exception handler located in a memory location accessible to the hard logic system irrespective of whether the bridge is open.
3. The method of claim 2 , wherein the exception handler is located in or proximate to the hard logic system.
4. The method of claim 1 , wherein the CLS comprises a programmable logic device.
5. The method of claim 1 , wherein the hard logic system is a bus master.
6. The method of claim 1 , wherein isolating the CLS comprises closing the bridge between the CLS and the hard logic system.
7. The method of claim 1 , wherein the run-time recovery process comprises reading an interconnect register to obtain an offending address, within the CLS, associated with the malformed interconnect response, and logging the offending address into a system log.
8. The method of claim 1 , wherein the CLS is configured in accordance with a first binary configuration file, and the run-time recovery process comprises making a determination whether or not a second, different, binary configuration file is accessible by the hard logic system.
9. The method of claim 8 , further comprising, when the determination is that the second binary configuration file is accessible, reconfiguring the CLS with the second binary file.
10. The method of claim 8 , further comprising, when the determination is that the second binary file is not accessible, safely shutting down the CLS.
11. An electronic circuit for monitoring transactions between a hard logic system and a configurable logic system (CLS), the CLS and the hard logic system being communicatively coupled by a bridge, the circuit being configured to:
receive an exception, the exception indicating that a malformed interconnect response has been output by the CLS;
clear all pending CLS transactions;
isolate the CLS; and
execute a run-time recovery process.
12. The circuit of claim 11 , wherein the circuit is configured to receive the exception at an exception handler located in a memory location accessible to the hard logic system irrespective of whether the bridge is open.
13. The circuit of claim 12 , wherein the exception handler is located in or proximate to the hard logic system.
14. The circuit of claim 11 , wherein the CLS comprises a programmable logic device.
15. The circuit of claim 11 , wherein the hard logic system is a bus master.
16. The circuit of claim 11 , wherein isolating the CLS comprises closing the bridge between the CLS and the hard logic system.
17. The circuit of claim 11 , wherein the run-time recovery process comprises reading an interconnect register to obtain an offending address, within the CLS, associated with the malformed interconnect response, and logging the offending address into a system log.
18. The circuit of claim 11 , wherein the CLS is configured in accordance with a first binary configuration file, and the run-time recovery process comprises making a determination whether or not a second, different, binary configuration file is accessible by the hard logic system.
19. The circuit of claim 18 , further comprising, when the determination is that the second binary configuration file is accessible, reconfiguring the CLS with the second binary file.
20. The circuit of claim 18 , further comprising, when the determination is that the second binary configuration file is not accessible, safely shutting down the CLS.