IP Library Granted Patent US 9,755,647
Granted Patent B1
US 9,755,647 · App. 15/294,588 · Granted Sep 5, 2017

Techniques for handling high voltage circuitry in an integrated circuit

Inventors: Andy Lee (San Jose, CA); Herman Schmit (Palo Alto, CA)
Assignee: Altera Corporation
H03K19/17724
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Quick Facts
Patent No.
US 9,755,647
App. No.
15/294,588
Granted
Sep 5, 2017
Kind
B1
Abstract

An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

Claims (31)

1. An integrated circuit formed using a semiconductor substrate, comprising:

a logic circuit within a first triple well structure within the semiconductor substrate that is supplied with a first bias voltage and operates at a first power supply voltage; and

a switch circuit within a second triple well structure within the semiconductor substrate that is electrically isolated from the first triple well structure and is supplied with a second bias voltage, wherein the switch circuit operates at a second power supply voltage, and wherein the switch circuit receives a control signal that controls the first bias voltage.

2. The integrated circuit defined in claim 1 , wherein the switch circuit comprises a driver circuit to selectively apply a signal to the logic circuit in response to the control signal and the first bias voltage.

3. The integrated circuit defined in claim 1 , wherein the second power supply voltage is greater than the first power supply voltage.

4. The integrated circuit defined in claim 1 , wherein the control signal has a first logic state and a second logic state, wherein the first logic state enables a programming operation of the integrated circuit, and wherein the second logic state disables the programming operation of the integrated circuit.

5. The integrated circuit defined in claim 4 , wherein the switch circuit controls the first bias voltage to be adjusted relative to the first power supply voltage when the control signal is in the first logic state.

6. The integrated circuit defined in claim 4 , wherein the switch circuit controls the first bias voltage to be adjusted relative to the second bias voltage when the control signal is in the second logic state.

7. The integrated circuit defined in claim 4 , wherein a portion of the logic circuit remains operational during the programming operation of the integrated circuit.

8. The integrated circuit defined in claim 1 , wherein the second bias voltage comprises a ground voltage.

9. The integrated circuit defined in claim 1 , wherein the logic circuit comprises an interconnect circuit.

10. The integrated circuit defined in claim 1 , wherein the logic circuit comprises an isolation circuit.

11. An integrated circuit comprising:

a logic circuit that operates in a first power supply domain, wherein the logic circuit receives a first bias signal on a first signal path; and

a switch circuit that operates in a second power supply domain that is different than the first power supply domain, wherein the switch circuit receives a second bias signal on a second signal path that is different than the first signal path and a control signal that controls a voltage of the first bias signal to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

12. The integrated circuit defined in claim 11 , wherein the switch circuit is electrically isolated from the logic circuit within a semiconductor substrate that forms the integrated circuit.

13. The integrated circuit defined in claim 11 , wherein the control signal has a first logic state and a second logic state, wherein the first logic state enables the programming operation of the integrated circuit and the second logic state disables the programming operation of the integrated circuit.

14. The integrated circuit defined in claim 13 , wherein the switch circuit controls the voltage of the first bias signal to be adjusted relative to the first power supply voltage when the control signal is in the first logic state.

15. The integrated circuit defined in claim 13 , wherein the switch circuit controls the voltage of the second bias signal to be adjusted relative to a voltage of the second power supply domain when the control signal is in the second logic state.

16. The integrated circuit defined in claim 11 , wherein the second bias signal comprises a ground signal.

17. The integrated circuit defined in claim 11 , wherein the first power supply domain comprises a first power supply voltage and the second power supply domain comprises a second power supply voltage that is greater than the first power supply voltage.

18. A method of operating an integrated circuit, comprising:

receiving a first bias signal using a logic circuit through a first signal path, wherein the logic circuit operates in a first power supply voltage;

receiving a second bias signal using a switch circuit through a second signal path that is different than the first signal path, wherein the switch circuit operates in a second power supply voltage that is higher than the first power supply voltage; and

controlling a voltage of the first bias signal to the logic circuit in response to a control signal to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

19. The method defined in claim 18 , wherein the control signal has a first logic state and a second logic state, wherein the first logic state enables the programming operation of the integrated circuit, and wherein the second logic state disables the programming operation of the integrated circuit, the method further comprising:

adjusting the voltage of the first bias signal relative to the first power supply voltage when the control signal is in the first logic state.

20. The method defined in claim 19 , further comprising:

adjusting the second power supply voltage relative to a predetermined voltage when the control signal is in the first logic state.

21. The method defined in claim 19 , further comprising:

adjusting the voltage of the first bias signal relative to a voltage of the second bias signal when the control signal is in the second logic state.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2016
From: LEE, ANDY; SCHMIT, HERMAN
To: ALTERA CORPORATION
Reel/Frame 040024/0208 →