Enhanced Adaptive Logic Circuitry with Improved Function Coverage and Packing Ability
To utilize unused or underused input and output pins without a large and undesirable impact on power and die area consumption, an adaptive logic module (ALM) of a programmable logic device may be implemented with an additional 2 LUT to improve small function packing density and wide function mapping coverage. The 2 LUT may also serve as a route-through to provide direct access to ALM registers with or without input inversion. The enhanced ALM may also use route-through configurations of the additional 2 LUT to improve the connectivity of the ALM inputs and outputs.
1 . Logic circuitry comprising:
a first lookup table (LUT) configurable to receive as inputs a set of inputs into the logic circuitry and output a set of outputs; and
a second LUT configurable to selectively receive as inputs:
one or more of the set of inputs into the logic circuitry; and
one or more of the set of outputs.
2 . The logic circuitry of claim 1 , wherein the first LUT comprises a 6-input fracturable LUT.
3 . The logic circuitry of claim 2 , wherein the second LUT comprises a 2-input LUT.
4 . The logic circuitry of claim 3 , wherein the first LUT and the second LUT are configurable to operate as two-function logic circuitry utilizing 8 logic inputs.
5 . The logic circuitry of claim 3 , wherein the first LUT and the second LUT are configurable to operate as three-function logic circuitry utilizing 8 logic inputs.
6 . The logic circuitry of claim 1 , wherein the second LUT comprises an output coupled to a first memory buffer and a second memory buffer.
7 . The logic circuitry of claim 6 , wherein the output of the second LUT is configurable to route an input signal to the first memory buffer or the second memory buffer.
8 . The logic circuitry of claim 1 , wherein the second LUT is configurable to selectively receive a first input of the set of inputs and a first output of the set of outputs via a first multiplexer and configurable to selectively receive a second input of the set of inputs and a second output of the set of outputs via a second multiplexer.
9 . The logic circuitry of claim 8 , wherein the first multiplexer is coupled to first enable circuitry and the second multiplexer is coupled to second enable circuitry.
10 . A method comprising:
identifying a plurality of lookup tables (LUTs) that may be implemented in an adaptive logic module (ALM) of a logic array block (LAB), the plurality of LUTs comprising:
a first LUT configurable to receive as inputs a set of inputs and output a set of outputs; and
a second LUT coupled to one or more inputs of the set of inputs and one or more outputs of the set of outputs;
directly inferring a first set of the plurality of LUTs; and
applying technology mapping to a second set of the plurality of LUTs and clustering the second set of the plurality of LUTs into one or more ALMs.
11 . The method of claim 10 , wherein the first LUT comprises a 6-input fracturable LUT.
12 . The method of claim 10 , wherein the second LUT is configurable to selectively receive a first input of the set of inputs and a first output of the set of outputs via a first multiplexer and configurable to selectively receive a second input of the set of inputs and a second output of the set of outputs via a second multiplexer.
13 . Logic circuitry comprising:
a first lookup table (LUT) configurable to provide a first LUT function and a second LUT function;
a second LUT comprising:
a first input configurable to receive a first signal associated with the first LUT function of the first LUT;
a second input configurable to receive a second signal associated with the second LUT function of the first LUT; and
an output coupled to a first memory buffer and a second memory buffer, wherein the second LUT is configurable to route a first input signal from the first LUT function to the first memory buffer, the second memory buffer, or both.
14 . The logic circuitry of claim 13 , wherein the second LUT is configurable to route a second input signal from the second LUT function to the first memory buffer, the second memory buffer, or both.
15 . The logic circuitry of claim 13 , wherein the first LUT comprises a 6-input fracturable LUT configurable to fracture to provide the first LUT function and the second LUT function.
16 . The logic circuitry of claim 15 , wherein the first LUT function, the second LUT function, or both comprise a 5-input LUTs.
17 . The logic circuitry of claim 13 , wherein the second LUT comprises a 2-input LUT.
18 . The logic circuitry of claim 13 , comprising:
a first multiplexer coupled to a first input of the first LUT, a first output of the first LUT, or both; and
a second multiplexer coupled to a second input of the first LUT, a second output of the first LUT, or both.
19 . The logic circuitry of claim 18 , wherein the first multiplexer and the second multiplexer are coupled to shared enable circuitry configurable to output a first configuration bit to select the first input of the first LUT or the first output of the first LUT and a second configuration bit to select the second input of the first LUT or the second output of the first LUT.
20 . The logic circuitry of claim 18 , wherein the first multiplexer is coupled to first enable circuitry configurable to output a first configuration bit to cause the first multiplexer to output to the second LUT and wherein the second multiplexer is coupled to second enable circuitry configurable to output a second configuration bit to cause the second multiplexer to output to the second LUT.