IP Library Granted Patent US 10,541,687
Granted Patent B2
US 10,541,687 · App. 15/942,919 · Granted Jan 21, 2020

Validating an image for a reconfigurable device

Inventors: Utkarsh Y. Kakaiya (Folsom, CA); Joshua D. Fender (East York, CA)
Assignee: Intel Corporation
H03K19/17768H03K19/17728H03K19/17764
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Quick Facts
Patent No.
US 10,541,687
App. No.
15/942,919
Granted
Jan 21, 2020
Kind
B2
Abstract

A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.

Claims (50)

1. A reconfigurable device comprising:

a reconfigurable circuit; and

reconfiguration logic to:

receive, via a policy interface, an image policy;

receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces;

validate the first reconfiguration image based on the image policy; and

in response to a determination that the first reconfiguration image is valid, reconfigure the reconfigurable circuit using the first reconfiguration image.

2. The reconfigurable device of claim 1 , wherein the reconfiguration logic comprises:

a user entity validator to validate the first reconfiguration interface using a user policy;

an image validator to validate the first reconfiguration image using the image policy; and

a circuit controller to reconfigure the reconfigurable circuit using the first reconfiguration image.

3. The reconfigurable device of claim 2 , wherein the user entity validator, the image validator, and the circuit controller are implemented in a hardware controller, and wherein the user policy is received via the policy interface.

4. The reconfigurable device of claim 3 , wherein the policy interface and the plurality of configuration interfaces are implemented in the hardware controller.

5. The reconfigurable device of claim 2 , wherein:

the user entity validator and the image validator are implemented in a software application; and

the circuit controller is implemented in a hardware controller.

6. The reconfigurable device of claim 2 , wherein:

the policy interface is implemented in a software application; and

the plurality of configuration interfaces are implemented in a hardware controller.

7. The reconfigurable device of claim 2 , wherein:

the user entity validator, the image validator, the policy interface, and the plurality of configuration interfaces are implemented in a software application; and

the circuit controller is implemented in a hardware controller.

8. The reconfigurable device of claim 2 , wherein:

the plurality of configuration interfaces are implemented in a software application; and

the user entity validator, the image validator, the circuit controller, and the policy interface are implemented in a hardware controller.

9. The reconfigurable device of claim 1 , wherein the reconfigurable circuit is a field-programmable gate array (FPGA).

10. The reconfigurable device of claim 1 , wherein the reconfiguration logic is to provide virtualized reconfiguration of the reconfigurable circuit.

11. A method comprising:

receiving, via a policy interface, an image policy associated with a reconfigurable circuit;

receiving a reconfiguration image via a first configuration interface of a plurality of configuration interfaces;

validating, by an image validator, the reconfiguration image using the image policy; and

reconfiguring, by a circuit controller, the reconfigurable circuit using the validated reconfiguration image.

12. The method of claim 11 , wherein the received reconfiguration image is encrypted, and further comprising decrypting the encrypted reconfiguration image.

13. The method of claim 11 , further comprising:

validating a signature of the reconfiguration image using the image policy.

14. The method of claim 11 , further comprising, prior to reconfiguring the reconfigurable circuit:

validating, by a user entity validator, the first reconfiguration interface using a user policy, wherein the user entity validator, the image validator, the circuit controller, the policy interface, and the plurality of configuration interfaces are implemented in a hardware controller.

15. The method of claim 11 , further comprising providing virtualized reconfiguration of the reconfigurable circuit via the plurality of configuration interfaces.

16. The method of claim 11 , wherein the reconfigurable circuit is a field-programmable gate array (FPGA).

17. A system comprising:

a reconfigurable circuit;

a policy interface to receive an image policy;

a plurality of configuration interfaces, including a first configuration interface to receive a reconfiguration image;

an image validator to validate the reconfiguration image based on the image policy; and

a circuit controller to reconfigure the reconfigurable circuit using the validated reconfiguration image.

18. The system of claim 17 , the image validator further to decrypt the reconfiguration image using the image policy.

19. The system of claim 17 , the image validator further to validate a signature of the reconfiguration image using the image policy.

20. The system of claim 17 , wherein the plurality of configuration interfaces are to provide a plurality of user entities with virtualized reconfiguration of the reconfigurable circuit.

21. The system of claim 17 , comprising a user entity validator to validate the first configuration interface based on a user policy, wherein the reconfigurable circuit, the user entity validator, the image validator, the circuit controller, the policy interface, and the plurality of configuration interfaces are included in a hardware processor.

22. The system of claim 17 , wherein the reconfigurable circuit is a field-programmable gate array (FPGA).

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2025
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 070159/0344 →
Continuity (2)
Continuation 15628888 · Jun 21, 2017
Related Publication 20190109593A1 · Apr 11, 2019