Methods and apparatus for reducing power consumption in memory circuitry by controlling precharge duration
Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.
1. A method of operating an integrated circuit, comprising:
during a decode time period, using a decoder circuit to address a memory cell;
using a precharge circuit to precharge a bit line that is coupled to the memory cell;
keeping the precharge circuit turned off during the decode time period; and
after the bit line is precharged, asserting a word line signal to access the memory cell.
2. The method defined in claim 1 , further comprising:
turning on the precharge circuit immediately following the decode time period.
3. The method defined in claim 1 , wherein the memory cell is also coupled to an additional bit line, the method further comprising:
precharging the bit line without precharging the additional bit line during a memory access operation.
4. The method defined in claim 1 , wherein the bit line comprises a read bit line, and wherein the memory cell is further coupled to at least one write bit line, the method further comprising:
precharging only the read bit line without precharging the at least one write bit line during a memory access operation.
5. The method defined in claim 1 , further comprising:
actively discharging the bit line while the precharge circuit is turned off.
6. An integrated circuit, comprising:
a first array of memory cells;
a second array of memory cells;
a word line that is coupled to the first array of memory cells and the second array of memory cells;
first precharge circuits that are coupled to the first array of memory cells;
second precharge circuits that are coupled to the second array of memory cells, wherein the first precharge circuits are activated to access at least one memory cell in the first array while the second precharge circuits are deactivated to reduce power consumption in the second array, and wherein the word line is driven high after the first precharge circuit is deactivated; and
a row decoder that determines which row in the first and second arrays to access during a decode time period, wherein the first and second precharge circuits are turned off during the decode time period.
7. The integrated circuit defined in claim 6 , wherein the memory cells in the first and second arrays are coupled to read and write bit lines, and wherein only the read bit lines are precharged during a memory access operation.
8. The integrated circuit defined in claim 6 , wherein the word line comprises a row line that is directly coupled to the memory cells in the first and second array of memory cells.
9. The integrated circuit defined in claim 6 , wherein each memory cell in the first and second arrays comprises eight transistors.