Optimizing IC design using retiming and presenting design simulation results as rescheduling optimization
A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.
1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of paths, each path comprising a plurality of nodes representing IC components comprising clocked elements and computational elements, the method comprising:
optimizing the timing performance of the IC design by retiming a set of paths, the retiming comprising skewing clock signals to a set of clocked elements by more than a clock period without changing a position of any clocked element relative to a position of the computational elements in the set of paths;
performing simulation on the optimized IC design;
providing a result of the simulation as a clock skew scheduled design of the IC design;
mapping the clock skew scheduled design into a retimed design by removing a first clocked element from the IC design and adding a second clocked element to the IC design; and
implementing the IC design using the retimed IC design.
2. The method of claim 1 , wherein
the retimed IC design receives a same input as the optimized IC design and generates a same output as the optimized IC design, the retimed IC design comprising at least one of (i) a clocked element removed from an input path of a computational element and a clocked element added to an output path of the combinational element and (ii) a clocked element removed from an output path of a computational element and a clocked element added to the input path of the combinational element.
3. The method of claim 1 , wherein mapping the optimized IC design into a retimed IC design further comprises:
identifying an amount of clock skew for each clocked element in the set of clocked elements;
identifying a position on the graph such that a delay of data signal travelling between the identified point and an input of a particular clocked element in the set of clocked elements is equal to the amount of clock skew for the particular clocked element;
removing the particular clocked element from the IC design, wherein the first clocked element comprises the particular clocked element; and
adding a replacement clocked element to the IC design at the identified position, wherein the second clocked element comprises the replacement clocked element.
4. The method of claim 1 , wherein providing a result of the simulation as a clock skew scheduling comprises:
providing arrival times of data and clock signals at inputs of the clocked and computational logic elements; and
providing available times of the data signals at output of the clocked elements and computational logic elements,
wherein a relative position of the clocked elements and the computational logic elements in the IC design prior to optimization is maintained in the simulation results.
5. The method of claim 1 , wherein each path in the set of paths starts from a timed source node in the graph and ends to a timed target node in the graph, each path in the set of paths comprising a plurality of clocked elements and a plurality of computational elements.
6. The method of claim 5 , wherein at least one path in the set of paths is a loop, wherein the source node and the target node in the loop are a same node.
7. The method of claim 5 , wherein a timed source node is one of a primary input through which the IC receives external inputs, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.
8. The method of claim 5 , wherein a timed target node is one of a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.
9. The method of claim 1 , wherein the graph further comprises a plurality of edges, each edge connecting two nodes without encompassing a third node, wherein an input path of a computational element is a path starting from the source node and ending to an edge connected to an input of the computational element, wherein an output path of a computational element is a path starting from an edge connected to an output of the computational element and ending to the target node.
10. The method of claim 1 , wherein each clocked element is one of a register, a flip-flop, and a latch.
11. The method of claim 1 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.
12. A non-transitory machine readable medium storing a program for optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of paths, each path comprising a plurality of nodes representing IC components comprising clocked elements and computational elements, the program executable by at least one processing unit, the program comprising sets of instructions for:
optimizing the timing performance of the IC design by retiming a set of paths, the retiming comprising skewing clock signals to a set of clocked elements by more than a clock period without changing a position of any clocked element relative to a position of the computational elements in the set of paths;
performing simulation on the optimized IC design; and
providing a result of the simulation as a clock skew scheduled design of the IC design;
mapping the clock skew scheduled design into a retimed design by removing a first clocked element from the IC design and adding a second clocked element to the IC design; and
implementing the IC design using the retimed IC design.
13. The non-transitory machine readable medium of claim 12 , wherein
the retimed IC design receives a same input as the optimized IC design and generates a same output as the optimized IC design, the retimed IC design comprising at least one of (i) a clocked element removed from an input path of a computational element and a clocked element added to an output path of the combinational element and (ii) a clocked element removed from an output path of a computational element and a clocked element added to the input path of the combinational element.
14. The non-transitory machine readable medium of claim 13 , wherein the set of instructions for mapping the optimized IC design into a retimed IC design comprises sets of instructions for:
identifying an amount of clock skew for each clocked element in the set of clocked elements;
identifying a position on the graph such that a delay of data signal travelling between the identified point and an input of a particular clocked element in the set of clocked elements is equal to the amount of clock skew for the particular clocked element;
removing the particular clocked element from the IC design, wherein the first clocked element comprises the particular clocked element; and
adding a replacement clocked element to the IC design at the identified position, wherein the second clocked element comprises the replacement clocked element.
15. The non-transitory machine readable medium of claim 12 , wherein the set of instructions for providing a result of the simulation as a clock skew scheduling comprises sets of instructions for:
providing arrival times of data and clock signals at inputs of the clocked and computational logic elements; and
providing available times of the data signals at output of the clocked elements and computational logic elements,
wherein a relative position of the clocked elements and the computational logic elements in the IC design prior to optimization is maintained in the simulation results.
16. The non-transitory machine readable medium of claim 12 , wherein each path in the set of paths starts from a timed source node in the graph and ends to a timed target node in the graph, each path in the set of paths comprising a plurality of clocked elements and a plurality of computational elements.
17. The non-transitory machine readable medium of claim 16 , wherein at least one path in the set of paths is a loop, wherein the source node and the target node in the loop are a same node.
18. The non-transitory machine readable medium of claim 16 , wherein a timed source node is one of a primary input through which the IC receives external inputs, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.
19. The non-transitory machine readable medium of claim 16 , wherein a timed target node is one of a primary output through which the IC sends outputs to external circuits, a storage element, and a node with timing constraints requiring a clock signal for the node to arrive at a fixed time.
20. The non-transitory machine readable medium of claim 12 , wherein the graph further comprises a plurality of edges, each edge connecting two nodes without encompassing a third node, wherein an input path of a computational element is a path starting from the source node and ending to an edge connected to an input of the computational element, wherein an output path of a computational element is a path starting from an edge connected to an output of the computational element and ending to the target node.
21. The non-transitory machine readable medium of claim 12 , wherein each clocked element is one of a register, a flip-flop, and a latch.
22. The non-transitory machine readable medium of claim 12 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.