Apparatus and methods for optimization of integrated circuits
View Patent ↗A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).
1. A system for computer-aided design (CAD) of an integrated circuit (IC) to implement a user's design by using resources of the integrated circuit (IC), the system comprising a computer, configured to optimize synthesis, placement, and/or routing of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC), wherein the computer is further configured to minimize a number of high-speed regions in the integrated circuit (IC) by monitoring a set of regions in the integrated circuit (IC) that are to be made high-speed regions by computing a first probability that a region in the set of regions will use the high-speed mode of operation.
2. The system according to claim 1 , wherein the computer is further configured to monitor the set of regions in the integrated circuit (IC) that are to be made high-speed regions by computing a second probability that a connection in the integrated circuit (IC) will use a region that operates in the high-speed mode of operation.
3. The system according to claim 2 , wherein the computer is further configured to compute a cost based on the first and second probabilities.
4. The system according to claim 1 , wherein the computer is further configured to compute a cost based on the first probability.
5. The system according to claim 4 , wherein the computer is further configured to incrementally update the first probability and the cost.
6. The system according to claim 1 , wherein the computer is further configured to propose a placement/routing alternative.
7. A computer-implemented method for implementing a user's design using resources of integrated circuit (IC), the method comprising optimizing, using the computer, synthesis, placement, and/or routing of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC), wherein the computer minimizes a number of high-speed regions in the integrated circuit (IC) by monitoring a set of regions in the integrated circuit (IC) that are to be made high-speed regions by computing a first probability that a region in the set of regions will use the high-speed mode of operation.
8. The method according to claim 7 , further comprising using the computer to monitor the set of regions in the integrated circuit (IC) that are to be made high-speed regions by computing a second probability that a connection in the integrated circuit (IC) will use a region that operates in the high-speed mode of operation.
9. The method according to claim 8 , further comprising using the computer to compute a cost based on the first and second probabilities.
10. The method according to claim 7 , further comprising using the computer to compute a cost based on the first probability.
11. The method according to claim 10 , further comprising using the computer to incrementally update the first probability and the cost.
12. The method according to claim 7 , wherein the computer proposes a placement/routing alternative.