Integrated circuit calibration system using general purpose processors
View Patent ↗In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.
1. An integrated circuit, comprising:
a general purpose processor circuit on the integrated circuit that generates a test input and an address signal after receiving an instruction to perform calibration; and
an analog interface circuit on the integrated circuit that receives the test input from the general purpose processor, that routes the test input to a physical medium attachment circuit identified by the address signal, and that generates a corresponding test output, wherein the analog interface circuit includes a bus circuit used only for calibration.
2. The integrated circuit defined in claim 1 , wherein the general purpose processor circuit comprises a non-reconfigurable circuit.
3. The integrated circuit defined in claim 1 , wherein the analog interface circuit comprises a transceiver circuit that transmits signals out of the integrated circuit and that receives signals from external circuitry.
4. The integrated circuit in defined claim 1 , wherein the analog interface circuit comprises the physical medium attachment (PMA) circuit and the physical medium attachment circuit receives the test input and outputs the test output based on the test input.
5. The integrated circuit defined in claim 1 , wherein the bus circuit includes 28 transmission paths to transfer 28 parallel signal bits.
6. The integrated circuit defined in claim 1 , wherein the bus circuit includes less than 50 transmission paths to transfer less than 50 parallel signal bits.
7. The integrated circuit defined in claim 4 , wherein the bus circuit conveys the test signal from the general purpose processor circuit to the physical medium attachment circuit, and wherein the bus circuit further conveys the test output from the physical medium attachment circuit to the general purpose processor circuit.
8. An integrated circuit, comprising:
a general purpose processor circuit on the integrated circuit that generates a calibration test input after receiving an instruction to perform calibration; and
an analog interface circuit on the integrated circuit comprising:
a calibration adapter circuit that implements a bus protocol and that receives the calibration test input from the general purpose processor circuit, wherein the calibration adapter circuit is a bus circuit that is used only for calibration purposes; and
a physical medium attachment circuit that receives the calibration test input from the calibration adapter circuit.
9. The integrated circuit defined in claim 8 , further comprising:
a register coupled between the calibration adapter circuit and a circuit in the analog interface circuit, wherein the register stores a calibration test output of the circuit.
10. The integrated circuit defined in claim 8 , wherein the calibration adapter circuit is further coupled to the other circuits in the analog interface circuit, wherein the other circuits are selected from one of: a Physical Coding System (PCS) circuit, a Dynamic Partial Reconfiguration Input/output (DPRIO) circuit and a Pipeline circuit.
11. The integrated circuit defined in claim 8 , wherein the calibration adapter circuit includes 28 transmission paths to transfer 28 parallel signal bits.
12. The integrated circuit defined in claim 8 , wherein the calibration adapter circuit includes less than 50 transmission paths to transfer less than 50 parallel signal bits.