Parallel decomposition of Reed Solomon umbrella codes
View Patent ↗Systems, methods, apparatus, and techniques are presented for processing a codeword. A Reed-Solomon mother codeword n symbols in length and having k check symbols is received, and the n symbols of the received Reed-Solomon mother codeword are separated into v Reed-Solomon daughter codewords, where v is a decomposition factor associated with the Reed-Solomon mother codeword. The v Reed-Solomon daughter codewords are processed in a respective set of v parallel processes to output v decoded codewords.
1. Codeword processing circuitry comprising:
receiver circuitry configured to receive a Reed-Solomon mother codeword n symbols in length and having k check symbols;
parallelization circuitry configured to separate the n symbols of the received Reed-Solomon mother codeword into v Reed-Solomon daughter codewords, wherein v is a decomposition factor associated with the received Reed-Solomon mother codeword; and
decoding circuitry configured to process the v Reed-Solomon daughter codewords in a respective set of v parallel processes to output v decoded codewords.
2. The codeword processing circuitry of claim 1 , further comprising identification circuitry configured to determine the decomposition factor v based, at least in part, on a channel quality over which the Reed-Solomon mother codeword is transmitted.
3. The codeword processing circuitry of claim 1 , wherein the decoding circuitry comprises a syndrome computation module configured to process symbols corresponding to each of the v Reed-Solomon daughter codewords to produce syndrome values corresponding to the received Reed-Solomon mother codeword.
4. The codeword processing circuitry of claim 1 , wherein the decoding circuitry comprises an error locator polynomial module configured to:
receive syndrome values corresponding to each of the v Reed-Solomon daughter codewords; and
process the received syndrome values in v parallel processes, each parallel process corresponding to a respective one of the v Reed-Solomon daughter codewords, to produce v error locator polynomials.
5. The codeword processing circuitry of claim 1 , wherein the decoding circuitry comprises an error locator polynomial module configured to:
receive syndrome values corresponding to each of the v Reed-Solomon daughter codewords; and
process the received syndrome values in v sequential processes, each sequential process corresponding to a respective one of the v Reed-Solomon daughter codewords, to produce v error locator polynomials.
6. The codeword processing circuitry of claim 1 , wherein the decoding circuitry comprises:
a Chien search and error calculation module configured to receive error locator polynomial coefficients corresponding to each of the v Reed-Solomon daughter codewords; and
process the received error locator polynomial coefficients in v parallel processes, each parallel process corresponding to a respective one of the v Reed-Solomon daughter codewords, to produce v output codewords.
7. The codeword processing circuitry of claim 1 , wherein each of the v Reed-Solomon daughter codewords is a (n/v, k/v) Reed-Solomon codeword.
8. The codeword processing circuitry of claim 1 , wherein the decomposition factor v is based, at least in part, on a network data throughput requirement.
9. A method comprising:
receiving a Reed-Solomon mother codeword n symbols in length and having k check symbols;
separating the n symbols of the received Reed-Solomon mother codeword into v Reed-Solomon daughter codewords, wherein v is a decomposition factor associated with the received Reed-Solomon mother codeword; and
processing the v Reed-Solomon daughter codewords in a respective set of v parallel processes to output v decoded codewords.
10. The method of claim 9 , wherein a determination of the decomposition factor v is based, at least in part, on a channel quality over which the Reed-Solomon mother codeword is transmitted.
11. The method of claim 9 , further comprising processing symbols corresponding to each of the v Reed-Solomon daughter codewords to produce syndrome values corresponding to the received Reed-Solomon mother codeword.
12. The method of claim 9 , further comprising:
receiving syndrome values corresponding to each of the v Reed-Solomon daughter codewords; and
processing the received syndrome values in v parallel processes, each parallel process corresponding to a respective one of the v Reed-Solomon daughter codewords, to produce v error locator polynomials.
13. The method of claim 9 , further comprising:
receiving syndrome values corresponding to each of the v Reed-Solomon daughter codewords; and
processing the received syndrome values in v sequential processes, each sequential process corresponding to a respective one of the v Reed-Solomon daughter codewords, to produce v error locator polynomials.
14. The method of claim 9 , further comprising:
receiving error locator polynomial coefficients corresponding to each of the v Reed-Solomon daughter codewords; and
processing the received error locator polynomial coefficients in v parallel processes, each parallel process corresponding to a respective one of the v Reed-Solomon daughter codewords, to produce v output codewords.
15. The method of claim 9 , wherein each of the v Reed-Solomon daughter codewords is a (n/v, k/v) Reed-Solomon codeword.