Compression of processor instructions

1. A method of providing a circuit having a custom processor, the method comprising:

providing the custom processor on the circuit, the custom processor including one or more or more functional units;

providing a program memory coupled with the custom processor through a decoder; and

storing a compressed instruction sequence in the program memory, the compressed instruction sequence corresponding to a predetermined instruction sequence, wherein said predetermined instruction sequence includes a plurality of instructions, each instruction of said predetermined instruction sequence comprising a first number of bits in respective bit positions and being executed by at least one of the functional units of the custom processor during a different clock cycle;

wherein the compressed instruction sequence is determined by:

performing at least one identification process on said instructions, in order to identify relationships between the bits in said bit positions among said instructions of said predetermined instruction sequence;

generating a compressed instruction sequence, comprising one compressed instruction corresponding to each instruction of the predetermined instruction sequence, and each compressed instruction comprising a second number of bits, based on the identified relationships between the bits in said bit positions in said instructions of said predetermined instruction sequence.

2. The method as claimed in claim 1 , wherein performing at least one identification process on said instructions includes identifying bit positions in said instructions of said predetermined instruction sequence which contain a same bit value in each instruction.

3. The method as claimed in claim 2 , wherein performing at least one identification process on said instructions includes identifying bit positions in said instructions of said predetermined instruction sequence which contain a binary “1” in each instruction.

4. The method as claimed in claim 2 , wherein performing at least one identification process on said instructions includes identifying bit positions in said instructions of said predetermined instruction sequence which contain a binary “0” in each instruction.

5. The method as claimed in claim 1 , wherein performing at least one identification process on said instructions includes identifying pairs of bit positions in said instructions of said predetermined instruction sequence which contain a same bit value as each other in each instruction.

6. The method as claimed in claim 1 , wherein performing at least one identification process on said instructions includes identifying pairs of bit positions in said instructions of said predetermined instruction sequence which contain opposite bit values in each instruction.

7. A processor, for performing at least one predetermined application, wherein the processor comprises a decoder and the decoder comprises:

an input for receiving a first number of bits of a compressed instruction for each of a plurality of compressed instructions, each bit having a value;

logic circuitry for converting said received first number of bits for each compressed instruction into a second number of bits of an uncompressed instruction, said second number being greater than said first number, wherein the logic circuitry includes circuitry for providing a fixed value for a same bit of each uncompressed instruction regardless of the values of the first number of bits received at the input for any compressed instruction; and

an output that supplies all of the bits of said uncompressed instructions to a functional unit of said processor, wherein the functional unit is adapted to act upon the uncompressed instructions sequentially and to perform one operation for each uncompressed instruction.

8. The processor as claimed in claim 7 , the decoder further comprising a high level signal supply, for providing the fixed value of a logic one as the fixed value of the same bit in each of said uncompressed instructions.

9. The processor as claimed in claim 7 , the decoder further comprising a low level signal supply, for providing the fixed value of a logic zero as the fixed value of the same bit in each of said uncompressed instructions.

10. The processor as claimed in claim 7 , wherein the logic circuitry comprises a separator, for receiving a first bit of said received first number of bits, and for supplying the value of said first bit as the value of a plurality of said second number of bits.

11. The processor as claimed in claim 7 , wherein the processor is implemented in a Programmable Logic Device.

12. The processor as claimed in claim 7 , wherein the processor is implemented in an Application Specific Integrated Circuit.

13. A processor, for performing at least one predetermined application, wherein the processor comprises a decoder and the decoder comprises:

an input for receiving a first number of bits of compressed instructions, each bit having a value;

logic circuitry for converting said received first number of bits into a second number of bits of uncompressed instructions, said second number being greater than said first number; and

an output that supplies all of said uncompressed instructions to a functional unit of said processor, wherein the functional unit is adapted to act upon the uncompressed instructions,

wherein the logic circuitry comprises an inverter, for receiving a first bit of said received first number of bits, and for supplying an inverse of the value of said first bit as the value of at least one of said second number of bits.

14. A processor, for performing at least one predetermined application, wherein the processor comprises a memory storing a compressed instruction sequence and one or more functional units coupled with the memory through a decoder, said compressed instruction sequence having been obtained by:

receiving a predetermined instruction sequence, each instruction of said predetermined instruction sequence comprising a first number of bits in respective bit positions and being executed by at least one of the functional units of the processor during a separate clock cycle;

performing at least one identification process on said instructions, in order to identify relationships between the bits in said bit positions among said instructions of said predetermined instruction sequence;

generating said compressed instruction sequence, comprising one compressed instruction corresponding to each instruction of the predetermined instruction sequence, and each compressed instruction comprising a second number of bits, based on the identified relationships between the bits in said bit positions in said instructions of said predetermined instruction sequence,

wherein said second number of bits is smaller than said first number of bits.

15. The processor as claimed in claim 14 , wherein each compressed instruction comprises a same second number of bits.

16. The processor as claimed in claim 14 , wherein the processor is implemented in a Programmable Logic Device.

17. The processor as claimed in claim 14 , wherein the processor is implemented in an Application Specific Integrated Circuit.

18. The processor as claimed in claim 14 , wherein performing at least one identification process on said instructions includes identifying bit positions in said instructions of said predetermined instruction sequence which contain a same bit value in each instruction.

19. The processor as claimed in claim 14 , wherein performing at least one identification process on said instructions includes identifying pairs of bit positions in said instructions of said predetermined instruction sequence which contain opposite bit values in each instruction.