Partial reconfiguration and in-system debugging
Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.
1. An apparatus comprising:
a first region of logic;
a second region of logic for configuring between a first logic design and a second logic design; and
a first port for receiving at least one signal from the second region of logic and providing the signal to the first region of logic, wherein the first logic design includes a first probe point associated with a first node of the first logic design, the second logic design includes a second probe point associated with a second node of the second logic design, and a signal associated with the first or second nodes provided to the first port based on the logic design configured in the second region of logic.
2. The apparatus of claim 1 , further comprising:
a logic analyzer coupled with the first port, the logic analyzer for providing the at least one signal to the first port.
3. The apparatus of claim 2 , wherein the logic analyzer is further for configuring between a first trigger condition associated with the first logic design and a second trigger condition associated with the second logic design, and wherein the trigger condition is configured based on the logic design configured in the second region of logic.
4. The apparatus of claim 2 , wherein the logic analyzer is further for providing a tag indicating a logic design implemented in the second region of logic to the first port.
5. The apparatus of claim 4 , further comprising:
a controller for providing the first logic design and the second logic design to the second region of logic, and wherein the controller is further for providing the tag associated with the logic design implemented in the second region of logic to the logic analyzer.
6. The apparatus of claim 1 , wherein the first logic design is associated with a first number of probe points, and the second logic design is associated with a second number of probe points, the first number different than the second number.
7. The apparatus of claim 2 , wherein the first port and the logic analyzer are implemented in the second region of logic.
8. A method for a device with a first region of logic and a second region of logic, the method comprising:
receiving, at the device, a first logic design and a second logic design;
configuring the second region of logic between the first logic design and the second logic design; and
implementing a first port for receiving at least one signal from the second region of logic and providing the signal to the first region of logic, wherein the first logic design includes a first probe point associated with a first node of the first logic design, the second logic design includes a second probe point associated with a second node of the second logic design, and a signal associated with the first or second nodes provided to the first port based on the logic design configured in the second region of logic.
9. The method of claim 8 , further comprising:
implementing a logic analyzer coupled with the first port, the logic analyzer for providing the at least one signal to the first port.
10. The method of claim 9 , wherein the logic analyzer is further for configuring between a first trigger condition associated with the first logic design and a second trigger condition associated with the second logic design, and wherein the trigger condition is configured based on the logic design configured in the second region of logic.
11. The method of claim 9 , wherein the logic analyzer is further for providing a tag indicating a logic design implemented in the second region of logic to the first port.
12. The method of claim 11 , further comprising:
providing, by a controller, the first logic design and the second logic design to the second region of logic, and wherein the controller is further for providing the tag associated with the logic design implemented in the second region of logic to the logic analyzer.
13. The method of claim 8 , wherein the first logic design is associated with a first number of probe points, and the second logic design is associated with a second number of probe points, the first number different than the second number.
14. The method of claim 8 , wherein the first port and the logic analyzer are implemented in the second region of logic.
15. A non-transitory tangible computer-readable storage medium storing instructions executable by a computing device with a first region of logic and a second region of logic to perform a method comprising:
receiving, at the device, a first logic design and a second logic design;
configuring the second region of logic between the first logic design and the second logic design; and
implementing a first port for receiving at least one signal from the second region of logic and providing the signal to the first region of logic, wherein the first logic design includes a first probe point associated with a first node of the first logic design, the second logic design includes a second probe point associated with a second node of the second logic design, and a signal associated with the first or second nodes provided to the first port based on the logic design configured in the second region of logic.
16. The non-transitory tangible computer-readable storage medium of claim 15 , further comprising:
implementing a logic analyzer coupled with the first port, the logic analyzer for providing the at least one signal to the first port.
17. The non-transitory tangible computer-readable storage medium of claim 16 , wherein the logic analyzer is further for configuring between a first trigger condition associated with the first logic design and a second trigger condition associated with the second logic design, and wherein the trigger condition is configured based on the logic design configured in the second region of logic.