IP Library Patent Application 18398760
Patent Application
App. No. 18/398,760

Temperature Gradient Control for Internal Regulated Supply

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Quick Facts
Patent No.
US None
App. No.
18/398,760
Abstract

Integrated circuits of the present disclosure may include a temperature dependent voltage source, a divider circuit, an adder circuit, and a voltage regulator. The divider circuit may apply a gradient tuning parameter to a first voltage provided by the temperature dependent voltage source to provide a second voltage to the adder circuit. The adder circuit may apply a level shift voltage to the second voltage to provide a third voltage to the voltage regulator. The voltage level may provide a fourth voltage to digital circuitry of an integrated circuit based on the third voltage.

Claims (27)

1 . An integrated circuit comprising:

a voltage regulator; and

voltage reference circuitry that includes a temperature dependent voltage source, a divider circuit, and an adder circuit, wherein the divider circuit is coupled to the voltage regulator by the adder circuit, and the divider circuit is coupled between the temperature dependent voltage source and the adder circuit.

2 . The integrated circuit of claim 1 , comprising digital circuitry coupled to the voltage reference circuitry by the voltage regulator.

3 . The integrated circuit of claim 1 , wherein the divider circuit includes a first leg with a first transistor and a second leg with a second transistor coupled in parallel with the first transistor.

4 . The integrated circuit of claim 3 , wherein a gate-to-source voltage of the first transistor is equal to a gate-to-source voltage of the second transistor.

5 . The integrated circuit of claim 3 , wherein the divider circuit includes an amplifier with an output coupled to a gate of the first transistor and to a gate of the second transistor.

6 . The integrated circuit of claim 3 , wherein one or more of the first transistor and the second transistor are coupled to a ground node by a variable resistance.

7 . The integrated circuit of claim 1 , wherein the adder circuit includes an amplifier with an amplifier input coupled to the divider circuit by a first resistance and to a level shift voltage by a second resistance.

8 . The integrated circuit of claim 1 , wherein the adder circuit includes an amplifier with an amplifier input coupled to a ground node by a first resistance and to the voltage regulator by a second resistance.

9 . An integrated circuit comprising:

a temperature dependent voltage source configured to provide a first voltage [V BE ];

a divider circuit coupled to the temperature dependent voltage source and configured to flatten a temperature gradient curve by providing a second voltage [V DIV ] based on the first voltage [V BE ]; and

a voltage regulator coupled to temperature dependent voltage source by the divider circuit, the voltage regulator configured to provide a third voltage [V CCHG ] to digital circuitry of the integrated circuit based on the second voltage [V DIV ].

10 . The integrated circuit of claim 9 , wherein the divider circuit is configured to provide the second voltage [V DIV ] by applying a gradient tuning parameter to the first voltage [V BE ] to change a temperature gradient of the first voltage [V BE ].

11 . The integrated circuit of claim 9 , wherein a gradient tuning parameter of the divider circuit tunes a slope of a temperature gradient of the second voltage [V DIV ].

12 . The integrated circuit of claim 9 , wherein the divider circuit includes a first leg with a first resistance and a second leg with a second resistance, and a gradient tuning parameter of the divider circuit is determined by one or more of a resistance value of the first resistance and a resistance value of the second resistance.

13 . The integrated circuit of claim 9 , wherein the divider circuit includes a gradient tuning parameter, and an inverse relationship exists between a value of the gradient tuning parameter and a temperature gradient of the second voltage [V DIV ].

14 . The integrated circuit of claim 9 , wherein in a voltage level of the second voltage [V DIV ] is less than a voltage level of the first voltage [V BE ].

15 . The integrated circuit of claim 9 , comprising an adder circuit configured to provide a fourth voltage [V REF ] based on the second voltage [V DIV ], and the voltage regulator configured to provide the third voltage [V CCHG ] based on the fourth voltage [V REF ].

16 . The integrated circuit of claim 15 , the adder circuit comprising an amplifier with an amplifier input coupled to the divider circuit by a first resistance and to a level shift voltage [V FIX ] by a second resistance.

17 . The integrated circuit of claim 16 , wherein a difference between a voltage level of the second voltage [V DIV ] and a voltage level of the fourth voltage [V REF ] is the level shift voltage [V FIX ].

18 . An integrated circuit comprising:

digital circuitry; and

voltage reference circuitry coupled to the digital circuitry by a voltage regulator, the voltage reference circuitry including a temperature dependent voltage source, a divider circuit, and an adder circuit, and the adder circuit coupled to the temperature dependent voltage source by the divider circuit.

19 . The integrated circuit of claim 18 , the divider circuit configured to provide a first voltage [V DIV ] based on a second voltage [V BE ] provided by the temperature dependent voltage source and a gradient tuning parameter with a value that is determined by a ratio of resistance values of resistors in the divider circuit.

20 . The integrated circuit of claim 18 , the adder circuit configured to provide a fourth voltage [V REF ] based on a first voltage [V DIV ] provided by the divider circuit and a level shift voltage [V FIX ] that has a voltage level determined by one or more of a designed operating voltage range of the digital circuitry and a temperature gradient of the first voltage.

Assignments (2)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2024
From: SIDDIQUI, MUHAMMAD YOUSUF; YELLEPEDDI, MANEESHA
To: ALTERA CORPORATION
Reel/Frame 067194/0667 →