Optimizing IC performance using sequential timing
View Patent ↗A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes several nodes that represent IC components. The method identifies a path in the graph that starts from a timed source node and ends at a timed target node. The path has several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to a set of clocked elements without changing the position of any clocked element relative to the position of the computational elements in the path. The clock signal of at least one clocked element is skewed by more than a period of the clock signal. The method implements the IC design by using the optimized IC design.
1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising:
identifying a path in the graph starting from a timed source node and ending at a timed target node, the path comprising a plurality of clocked elements and a plurality of computational elements, wherein the path fails to satisfy timing constraints;
optimizing the timing performance of the IC design by skewing clock signals to a set of clocked elements in the plurality of clocked elements without changing a position of any clocked element relative to a position of the computational elements in the path, wherein the clock signal of at least one clocked element is skewed by more than a period of said clock signal; and
implementing the IC design using the optimized IC design.
2. The method of claim 1 , wherein the graph further comprises a plurality of edges, each edge connecting two nodes without encompassing a third node, wherein changing a position of any clocked element relative to a position of the computational elements in the path comprises (i) adding or removing clocked elements from an input path of a computational element and (ii) adding or removing clocked elements from an output path of a computational element, wherein an input path of a computational element is a path starting from the source node and ending at an edge connected to an input of the computational element, wherein an output path of a computational element is a path starting from an edge connected to an output of the computational element and ending at the target node.
3. The method of claim 1 , wherein the identified path is a loop, wherein the source node and the target node are a same node.
4. The method of claim 1 , wherein each clocked element is one of a register, a flip-flop, and a latch.
5. The method of claim 1 , wherein a timed source node is one of a primary input through which the IC receives external inputs, a storage element, and a node with additional timing constraints requiring a clock signal for the node to arrive at a fixed time.
6. The method of claim 1 , wherein a timed target node is one of a primary output through which the IC sends outputs to external circuits, a storage element, and a node with additional timing constraints requiring a clock signal for the node to arrive at a fixed time.
7. The method of claim 1 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.
8. A non-transitory machine readable medium storing a program for optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the program executable by at least one processing unit, the program comprising sets of instructions for:
identifying a path in the graph starting from a timed source node and ending at a timed target node, the path comprising a plurality of clocked elements and a plurality of computational elements, wherein the path fails to satisfy timing constraints;
optimizing the timing performance of the IC design by skewing clock signals to a set of clocked elements in the plurality of clocked elements without changing a position of any clocked element relative to a position of the computational elements in the path, wherein the clock signal of at least one clocked element is skewed by more than a period of said clock signal; and
implementing the IC design using the optimized IC design.
9. The non-transitory machine readable medium of claim 8 , wherein the graph further comprises a plurality of edges, each edge connecting two nodes without encompassing a third node, wherein changing a position of any clocked element relative to a position of the computational elements in the path comprises (i) adding or removing clocked elements from an input path of a computational element and (ii) adding or removing clocked elements from an output path of a computational element, wherein an input path of a computational element is a path starting from the source node and ending at an edge connected to an input of the computational element, wherein an output path of a computational element is a path starting from an edge connected to an output of the computational element and ending at the target node.
10. The non-transitory machine readable medium of claim 8 , wherein the identified path is a loop, wherein the source node and the target node are a same node.
11. The non-transitory machine readable medium of claim 8 , wherein each clocked element is one of a register, a flip-flop, and a latch.
12. The non-transitory machine readable medium of claim 8 , wherein a timed source node is one of a primary input through which the IC receives external inputs, a storage element, and a node with additional timing constraints requiring a clock signal for the node to arrive at a fixed time.
13. The non-transitory machine readable medium of claim 8 , wherein a timed target node is one of a primary output through which the IC sends outputs to external circuits, a storage element, and a node with additional timing constraints requiring a clock signal for the node to arrive at a fixed time.
14. The non-transitory machine readable medium of claim 8 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.
15. A device comprising:
a set of processing units; and
a non-transitory machine readable medium storing a program for execution by at least one of the processing units, the program for optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the program executable by at least one processing unit, the program comprising sets of instructions for:
identifying a path in the graph starting from a timed source node and ending at a timed target node, the path comprising a plurality of clocked elements and a plurality of computational elements, wherein the path fails to satisfy timing constraints;
optimizing the timing performance of the IC design by skewing clock signals to a set of clocked elements in the plurality of clocked elements without changing a position of any clocked element relative to a position of the computational elements in the path, wherein the clock signal of at least one clocked element is skewed by more than a period of said clock signal; and
implementing the IC design using the optimized IC design.
16. The device of claim 15 , wherein the graph further comprises a plurality of edges, each edge connecting two nodes without encompassing a third node, wherein changing a position of any clocked element relative to a position of the computational elements in the path comprises (i) adding or removing clocked elements from an input path of a computational element and (ii) adding or removing clocked elements from an output path of a computational element, wherein an input path of a computational element is a path starting from the source node and ending at an edge connected to an input of the computational element, wherein an output path of a computational element is a path starting from an edge connected to an output of the computational element and ending at the target node.
17. The device of claim 15 , wherein the identified path is a loop, wherein the source node and the target node are a same node.
18. The device of claim 15 , wherein each clocked element is one of a register, a flip-flop, and a latch.
19. The device of claim 15 , wherein a timed source node is one of a primary input through which the IC receives external inputs, a storage element, and a node with additional timing constraints requiring a clock signal for the node to arrive at a fixed time.
20. The device of claim 15 , wherein a timed target node is one of a primary output through which the IC sends outputs to external circuits, a storage element, and a node with additional timing constraints requiring a clock signal for the node to arrive at a fixed time.
21. The device of claim 15 , wherein the IC is one of an application-specific integrated circuit (ASIC), a structured ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a complex programmable logic device (CPLD), a system on chip (SOC), a system-in-package (SIP), and a reconfigurable IC.