Data interleaving and deinterleaving involving concatenation of words read from storage
View Patent ↗An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory is described. In one embodiment, the apparatus includes a read circuit for selecting bits of the stored sequence and forming the selected bits into a word, and a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of words produced by the read circuit. The technique can also be used to achieve interleaving, rather than de-interleaving, of a data sequence.
1. An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory, the apparatus comprising:
a read circuit for selecting bits of the sequence of bits stored in the memory and forming the selected bits into an intermediate word; and
a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of intermediate words produced by the read circuit.
2. An apparatus according to claim 1 , wherein a section of the intermediate word produced by the read circuit which is not used to produce the word of the de-interleaved sequence is stored for use in producing a later word of the de-interleaved sequence.
3. An apparatus according to claim 1 , wherein the memory is spread over a plurality of separate memory instances.
4. An apparatus according to claim 1 , wherein the logic network comprises:
a marshalling logic circuit for selecting and positioning bits to be de-interleaved; and
a concatenation logic circuit for concatenating the bits selected by the marshalling logic circuit to produce the word of the de-interleaved sequence.
5. An apparatus according to claim 4 , wherein the marshalling logic circuit comprises a masking element for selecting bits to be de-interleaved.
6. An apparatus according to claim 4 , wherein the marshalling logic circuit comprises a shifting element for shifting bits to be de-interleaved.
7. An apparatus according to claim 4 , wherein the concatenation logic circuit comprises a register for storing a section of the intermediate word formed by the read circuit which is not used to produce the word of the de-interleaved sequence.
8. An apparatus according to claim 5 , wherein the marshalling logic circuit comprises a further masking element for selecting positioned bits.
9. An apparatus according to claim 1 , wherein the logic network comprises a plurality of marshalling logic circuits, each marshalling logic circuit being configured to select and position bits of a different word formed by the read circuit.
10. An apparatus according to claim 9 , wherein each of the marshalling logic circuits is substantially identical.
11. A method of producing a word of a de-interleaved sequence of bits from a stored sequence of bits, the method comprising:
selecting bits of the stored sequence and forming the selected bits into an intermediate word; and
concatenating sections of a plurality of intermediate words so formed to produce the word of the de-interleaved sequence.
12. A method according to claim 11 , wherein a section of the intermediate word formed from the stored sequence of bits which is not used to produce the word of the de-interleaved sequence is stored for use in producing a later word of the de-interleaved sequence.
13. A method according to claim 11 , wherein the stored sequence of bits is stored in a memory which is spread over a plurality of separate memory instances.
14. A method according to claim 11 , wherein:
bits to be de-interleaved are selected and positioned by a marshalling logic circuit; and
the bits selected by the marshalling logic circuit are concatenated by a concatenation logic circuit to produce the word of the de-interleaved sequence.
15. A method according to claim 14 , wherein bits to be de-interleaved are selected by a masking element.
16. A method according to claim 14 , wherein the bits to be de-interleaved are positioned by a shifting element.
17. A method according to claim 14 , wherein a section of the intermediate word formed by the read circuit which is not used to produce the word of the de-interleaved sequence is stored in a register of the marshalling logic circuit.
18. A method according to claim 15 , wherein positioned bits are selected by a further masking element.
19. A method according to claim 11 , wherein a plurality of marshalling logic circuits are operative to select and position bits of a different word formed from the stored sequence.
20. A method according to claim 19 , wherein each of the marshalling logic circuits is substantially identical.
21. An apparatus for producing a word of length s bits of a de-interleaved version of a data block comprising a series of original words of length p bits, the apparatus comprising:
a) a memory arranged to store the data block;
b) a read circuit arranged to read, from the memory, a bit of an original word at an end of the series, read each succeeding p th bit in the series to read s bits altogether and deliver the s bits as an intermediate word; and
c) a logic network arranged to concatenate sections of intermediate words delivered by the read circuit to produce said word of the de-interleaved version of said data block.
22. A method of producing a word of length s bits of a de-interleaved version of a data block comprising a series of original words of length p bits, the method comprising:
a) storing the data block in a memory;
b) reading, from the memory, a bit of an original word at an end of the series, reading each succeeding p th bit in the series to read s bits altogether and delivering the s bits as an intermediate word; and
c) concatenating sections of intermediate words to produce said word of the de-interleaved version of said data block.