Configurable storage elements

1. An integrated circuit (“IC”) comprising:

a row of configurable logic circuits for configurably performing a plurality of logic operations based on configuration data;

a plurality of configuration retrieval circuits for providing the configuration data to the row of configurable logic circuits; and

a row configuration controller for forcing the plurality of configuration retrieval circuits to output a particular configuration value as the provided configuration data to the row of configurable logic circuits based on a user signal received at runtime.

2. The IC of claim 1 , wherein the particular configuration value configures the row of configurable logic circuits to save power.

3. The IC of claim 1 , wherein the particular configuration value configures the row of configurable logic circuits to prevent bit flickering.

4. The IC of claim 3 , wherein the bit flickering is prevented by forcing a routing circuit to select a signal from a closed storage element as output.

5. The IC of claim 3 , wherein the bit flickering is prevented by forming a feedback path from an output of a routing circuit to an input of the routing circuit.

6. The IC of claim 1 , wherein the user signal is asserted during a set of sub-cycles to disable the row of configurable logic circuits during the set of sub-cycles.

7. The IC of claim 1 , wherein the row configuration controller provides a set of select signals to the plurality of configuration retrieval circuits based on the received user signal, wherein the set of select signals force the plurality of configuration retrieval circuits to output the particular configuration value.

8. The IC of claim 7 , wherein the user signal is asserted in a first sub-cycle and the set of select signals are frozen in consecutive sub-cycles subsequent to the first sub-cycle to save power.

9. The IC of claim 1 , wherein the particular configuration value is a default ground value.

10. A method comprising:

identifying a set of logic elements in an integrated circuit (IC) design that is disabled during a set of sub-cycles;

identifying a user signal that defines the set of sub-cycles;

assigning the identified set of logic elements to a row of configurable circuits; and

routing the user signal to disable the row of configurable circuits during the set of sub-cycles.

11. The method of claim 10 further comprising identifying the row of configurable circuits to perform the set of logic elements.

12. The method of claim 10 , wherein the row of configurable circuits perform a plurality of logic operations based on configuration data, wherein a plurality of configuration retrieval circuits provides the configuration data to the row of configurable circuits.

13. The method of claim 12 , wherein the user signal is routed to a row configuration controller to force the plurality of configuration retrieval circuits to output a particular configuration value as the provided configuration data to the row of configurable circuits.

14. The method of claim 10 , wherein the IC design defines operations of the set of logic elements, wherein the defined operations are performed by the row of configurable circuits.

15. A non-transitory computer readable medium storing a computer program for configuring an integrated circuit (IC) based on a user design, the computer program executable on one or more processing units, the computer program comprising sets of instructions for:

identifying a set of logic elements in the user design that is inactive during a set of clock cycles;

identifying a user signal that disables the set of logic elements during the set of clock cycles;

assigning the set of logic elements to a row of configurable circuits; and

routing the identified user signal to put the row of configurable circuits into a power saving mode during the set of sub-cycles.

16. The non-transitory computer readable medium of claim 15 , wherein the set of clock cycles are consecutive clock cycles.

17. The non-transitory computer readable medium of claim 15 , wherein the set of instructions for assigning the set of logic elements to the row of configurable circuits comprise a set of instructions for identifying a row of configurable circuits that can implement the set of logic elements.

18. The non-transitory computer readable medium of claim 17 , wherein the set of instructions for routing the identified user signal comprises a set of instructions for routing the identified user signal to a row configuration controller for the identified row of configurable circuits.

19. The non-transitory computer readable medium of claim 18 , wherein the row configuration controller uses the identified user signal to force a plurality of configuration retrieval circuits to output a particular configuration value for the row of configurable circuits.

20. The non-transitory computer readable medium of claim 15 , wherein the row of configurable circuits is reconfigured every clock cycle.

21. The non-transitory computer readable medium of claim 15 , wherein the set of instructions for assigning the set of logic elements to a row of configurable circuits comprise a set of instructions for defining a set of configuration data for configuring the row of configurable circuits to perform operations of the set of logic elements.

22. The non-transitory computer readable medium of claim 15 , wherein the set of instructions for routing the user signal comprises a set of instructions for defining a set of configuration data for configuring one or more configurable routing circuits to route the user signal to a row configuration controller for the row of configurable circuits.