Techniques for generating pulse-width modulation data

1. An integrated circuit comprising:

a control circuit that generates parallel pulse-width modulation data in first parallel pulse-width modulation signals;

a first-in first-out circuit that stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals, wherein the first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals; and

a serializer circuit that converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.

2. The integrated circuit of claim 1 , wherein the control circuit is programmed by software or configuration data to generate the parallel pulse-width modulation data.

3. The integrated circuit of claim 2 , wherein the control circuit is reprogrammable to generate the parallel pulse-width modulation data based on different protocols.

4. The integrated circuit of claim 1 , wherein the first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals in response to a first clock signal, and wherein the first-in first-out circuit outputs the stored parallel pulse-width modulation data in the second parallel pulse-width modulation signals in response to a second clock signal.

5. The integrated circuit of claim 4 , wherein the control circuit generates the parallel pulse-width modulation data in response to the first clock signal, and wherein the serializer circuit converts the parallel pulse-width modulation data to the serial pulse-width modulation data in response to the second clock signal and in response to a third clock signal.

6. The integrated circuit of claim 1 , wherein the first-in first-out circuit generates a full signal that is provided to the control circuit, and wherein the control circuit only provides the parallel pulse-width modulation data to the first-in first-out circuit in the first parallel pulse-width modulation signals in response to the full signal indicating that the first-in first-out circuit is not full.

7. The integrated circuit of claim 1 , wherein the serializer circuit varies a duty cycle of the serial pulse-width modulation signal based on changes in the parallel pulse-width modulation data generated by the control circuit.

8. The integrated circuit of claim 1 , further comprising:

an interface circuit that receives a regulated voltage from a voltage regulator circuit, wherein the interface circuit generates digital signals that indicate the regulated voltage, wherein the digital signals are provided to the control circuit, and wherein the control circuit adjusts the parallel pulse-width modulation data based on changes in the regulated voltage generated by the voltage regulator circuit.

9. The integrated circuit of claim 1 , wherein the control circuit comprises programmable logic circuits, and wherein the integrated circuit is a programmable logic integrated circuit.

10. An integrated circuit comprising:

a control circuit that generates parallel pulse-width modulation data in first parallel pulse-width modulation signals in response to a first clock signal;

a first-in first-out circuit that stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals in response to the first clock signal, wherein the first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals in response to a second clock signal; and

a serializer circuit that converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal in response to the second clock signal.

11. The integrated circuit of claim 10 , wherein the serializer circuit converts the parallel pulse-width modulation data to the serial pulse-width modulation data in response to a third clock signal, and wherein a frequency of the third clock signal is greater than frequencies of the first and second clock signals.

12. The integrated circuit of claim 10 , wherein the control circuit is reprogrammable to generate the parallel pulse-width modulation data based on different pulse-width modulation protocols.

13. The integrated circuit of claim 10 , further comprising:

an interface circuit that receives a regulated voltage from a voltage regulator circuit, wherein the interface circuit generates digital signals that indicate the regulated voltage, wherein the digital signals are provided to the control circuit, and wherein the control circuit adjusts the parallel pulse-width modulation data based on changes in the regulated voltage as indicated by the digital signals.

14. The integrated circuit of claim 10 , wherein the control circuit comprises programmable logic circuits, and wherein the integrated circuit is a programmable logic integrated circuit.

15. The integrated circuit of claim 10 , wherein the serializer circuit varies a duty cycle of the serial pulse-width modulation signal based on changes in the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals.

16. A method comprising:

generating parallel pulse-width modulation data in first parallel pulse-width modulation signals using a control circuit in an integrated circuit;

storing the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals in a first-in first-out circuit in the integrated circuit in response to a first clock signal;

outputting the stored parallel pulse-width modulation data from the first-in first-out circuit in second parallel pulse-width modulation signals in response to a second clock signal; and

converting the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal using a serializer circuit in the integrated circuit.

17. The method of claim 16 , wherein the control circuit generates the parallel pulse-width modulation data in response to the first clock signal, and wherein the serializer circuit converts the parallel pulse-width modulation data to the serial pulse-width modulation data in response to the second clock signal.

18. The method of claim 16 , further comprising:

generating digital signals that indicate a regulated voltage received from a voltage regulator circuit using an interface circuit in the integrated circuit;

providing the digital signals to the control circuit; and

adjusting the parallel pulse-width modulation data based on changes in the regulated voltage as indicated by the digital signals using the control circuit.

19. The method of claim 16 , further comprising:

programming the control circuit to generate the parallel pulse-width modulation data based on a first pulse-width modulation protocol; and

reprogramming the control circuit to generate the parallel pulse-width modulation data based on a second pulse-width modulation protocol.

20. The method of claim 16 , further comprising:

varying a duty cycle of the serial pulse-width modulation signal based on changes in the parallel pulse-width modulation data using the serializer circuit.