IP Library › Granted Patent US 7,420,390
Granted Patent B1
US 7,420,390 · App. 11/328,407 · Granted Sep 2, 2008

Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size

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Quick Facts
Patent No.
US 7,420,390
App. No.
11/328,407
Granted
Sep 2, 2008
Kind
B1
Abstract

A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.

Claims (45)

1. A field programmable gate array (FPGA), comprising:

a plurality of programmable logic blocks to implement one or more logic functions; and

a plurality of independent registers programmable to support any one of the plurality of programmable logic blocks to provide synchronization for pipelining signals on the FPGA, wherein each of the plurality of independent registers includes an input line independent of any programmable logic block.

2. The FPGA of claim 1 , wherein the plurality of programmable logic blocks make up a logic array block.

3. The FPGA of claim 1 , wherein the plurality of programmable logic blocks make up a subset of a logic array block.

4. The FPGA of claim 1 , wherein the plurality of programmable logic blocks comprises combinational cells and registers.

5. The FPGA of claim 1 , wherein each of the plurality of independent registers is programmable to receive a shared input from one of the plurality of programmable logic blocks.

6. The FPGA of claim 1 , wherein each of the plurality of independent registers is programmable to receive an output from one of the plurality of programmable logic blocks.

7. The FPGA of claim 1 , wherein the plurality of independent registers is programmable to implement a pipelined carry when the plurality of programmable logic blocks are programmed to implement an adder circuit.

8. The FPGA of claim 1 , further comprising a switching network that includes one or more multiplexers to program the first plurality of independent registers.

9. The FPGA of claim 1 , wherein a programmable logic block comprises a four input look up table (LUT) and a flip-flop.

10. The FPGA of claim 1 , wherein the input line is a direct cascade connection from a register.

11. The FPGA of claim 1 , wherein the programmable logic block is fracturable into a plurality of configurations.

12. The FPGA of claim 1 , wherein the plurality of programmable logic blocks make up a logic array block.

13. The FPGA of claim 1 , wherein the plurality of programmable logic blocks make up a subset of a logic array block.

14. The FPGA of claim 1 , wherein the plurality of programmable logic blocks comprises combinational cells and registers.

15. The FPGA of claim 1 , wherein the programmable logic block is fracturable into a plurality of configurations.

16. A field programmable gate array (FPGA), comprising:

a plurality of programmable logic blocks to implement one or more logic functions; and

a plurality of independent registers unassigned to any specific one of the plurality of programmable logic blocks and programmable to support any one of the plurality of programmable logic blocks, wherein each of the plurality of independent registers is programmable to receive one of a shared input and a shared output from one of the plurality of programmable logic blocks.

17. The FPGA of claim 16 , wherein the plurality of independent registers are programmable to implement a pipelined carry when the plurality of programmable logic blocks are programmed to implement an adder circuit.

18. The FPGA of claim 16 , wherein the plurality of programmable logic blocks make up a logic array block.

19. The FPGA of claim 16 , wherein the plurality of programmable logic blocks make up a subset of a logic array block.

20. The FPGA of claim 16 , wherein the plurality of programmable logic blocks comprises combinational cells and registers.

21. The FPGA of claim 16 , wherein each of the plurality of independent registers includes an input line independent of any programmable logic block.

22. The FPGA of claim 21 , wherein the input line is a direct cascade connection from a register.

23. The FPGA of claim 16 , further comprising a switching network that includes one or more multiplexers to program the first plurality of independent registers.

24. The FPGA of claim 16 , wherein a programmable logic block comprises a four input look up table (LUT) and a flip-flop.

25. The FPGA of claim 16 , wherein the programmable logic block is fracturable into a plurality of configurations.

26. A field programmable gate array (FPGA), comprising:

a plurality of programmable logic blocks to implement one or more logic functions; and

a plurality of independent registers programmable to support any one of the plurality of programmable logic blocks, wherein each of the plurality of independent registers includes an input line that is programmable to receive one of a first input independent of any programmable logic block, and a second input from a direct cascade connection from a register.

27. A field programmable gate array (FPGA), comprising:

a plurality of programmable logic blocks to implement one or more logic functions; and

a plurality of independent registers programmable to support any one of the plurality of programmable logic blocks to provide synchronization for pipelining signals on the FPGA, wherein the plurality of independent registers is programmable to implement a pipelined carry when the plurality of programmable logic blocks are programmed to implement an adder circuit.

28. The FPGA of claim 27 , wherein the plurality of programmable logic blocks make up a logic array block.

29. The FPGA of claim 27 , wherein the plurality of programmable logic blocks make up a subset of a logic array block.

30. The FPGA of claim 28 , wherein the plurality of programmable logic blocks comprises combinational cells and registers.

31. The FPGA of claim 28 , wherein each of the plurality of independent registers includes an input line independent of any programmable logic block.

32. The FPGA of claim 29 , wherein each of the plurality of independent registers is programmable to receive a shared input from one of the plurality of programmable logic blocks.

33. The FPGA of claim 30 , wherein each of the plurality of independent registers is programmable to receive an output from one of the plurality of programmable logic blocks.

34. The FPGA of claim 30 , wherein the plurality of independent registers is programmable to implement a pipelined carry when the plurality of programmable logic blocks are programmed to implement an adder circuit.

35. The FPGA of claim 31 , further comprising a switching network that includes one or more multiplexers to program the first plurality of independent registers.

36. The FPGA of claim 31 , wherein a programmable logic block comprises a four input look up table (LUT) and a flip-flop.

37. The FPGA of claim 32 , wherein the input line is a direct cascade connection from a register.

Assignments (1)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →