MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de) compressed data streams.
1 . An integrated circuit comprising:
data utilization circuitry; and
inter-die input/output circuitry configurable to communicate data to or from the data utilization circuitry to a second integrated circuit within the same package as the integrated circuit in:
a first mode in which a read clock signal or a write clock signal has a first frequency; and
a second mode in which the read clock signal or the write clock signal has a second frequency that is different than the first frequency.
2 . The integrated circuit of claim 1 , wherein the inter-die input/output circuitry is configurable to couple to second inter-die input/output circuitry of the second integrated circuit within the same package as the integrated circuit.
3 . The integrated circuit of claim 2 , wherein the inter-die input/output circuitry is configurable to couple to:
third inter-die input/output circuitry of a third integrated circuit within the same package as the integrated circuit; and
fourth inter-die input/output circuitry of a fourth integrated circuit within the same package as the integrated circuit.
4 . The integrated circuit of claim 2 , wherein the inter-die input/output circuitry is configurable to operate in the first mode while the second inter-die input/output circuitry is also operating in the first mode and to operate in the second mode while the second inter-die input/output circuitry is also operating in the second mode.
5 . The integrated circuit of claim 2 , wherein the inter-die input/output circuitry is configurable to operate in the first mode while the second inter-die input/output circuitry is operating in the second mode and to operate in the second mode while the second inter-die input/output circuitry is operating in the first mode.
6 . The integrated circuit of claim 1 , wherein the inter-die input/output circuitry is configurable to switch between operating in the first mode and the second mode.
7 . The integrated circuit of claim 1 , wherein the data utilization circuitry comprises a processor.
8 . The integrated circuit of claim 1 , wherein the data utilization circuitry comprises programmable logic circuitry.
9 . The integrated circuit of claim 1 , wherein the data utilization circuitry comprises transceiver circuitry.
10 . The integrated circuit of claim 1 , wherein the inter-die input/output circuitry is configurable to generate the read clock signal and the write clock signal based on the same clock source.
11 . The integrated circuit of claim 1 , wherein the second frequency is double the first frequency.
12 . A method comprising:
selecting between a first mode and a second mode; and
communicating from a first die of a package to a second die of the package based on write and read clock signals, wherein the write and read clock signals have the same frequency in the first mode and the write and read clock signals have different frequencies in the second mode.
13 . The method of claim 12 , wherein the write and read clock signals have different frequencies in the second mode, wherein a first one of the write clock signal or the read clock signal has a first frequency and a second one of the write clock signal or the read clock signal has a second frequency, wherein the second frequency is double the first frequency.
14 . The method of claim 12 , wherein communicating, in the second mode, comprises performing data width compression.
15 . The method of claim 14 , wherein communicating, in the first mode, comprises not performing the data width compression.
16 . A multi-die device comprising:
a first die having first inter-die input/output circuitry; and
a second die having second inter-die input/output circuitry communicatively coupled to the first inter-die input/output circuitry, wherein the second inter-die input/output circuitry is configurable to operate in:
a first mode in which a read clock frequency or a write clock frequency has a first frequency; and
a second mode in which the read clock frequency or the write clock frequency has a second frequency different from the first frequency.
17 . The multi-die device of claim 16 , wherein the second inter-die input/output circuitry comprises a transmit buffer configurable to compress data transmitted while operating in the in the second mode.
18 . The multi-die device of claim 16 , wherein the second inter-die input/output circuitry comprises a receive buffer configurable to decompress data received while operating in the in the second mode.
19 . The multi-die device of claim 16 , wherein:
in the first mode, the read clock frequency has the first frequency; and
in the second mode, the read clock frequency has the second frequency.
20 . The multi-die device of claim 16 , wherein the second frequency is double the first frequency.